A disclosed amplifier circuit is capable of changing a gain to amplify an input signal according to a control signal. The amplifier circuit comprises a differential amplifier circuit adapted to receive and amplify the input signal to output the amplified input signal as an output signal, a first resistance and one or more second resistances connected to the differential amplifier circuit and adapted to set the gain, and one or more gain control circuits adapted to change the gain by controlling ...

A network structure configures a blocking network having constraint against such a combination of said network input terminal and network output terminal as to make it unfeasible to further connect, when connecting first network input terminals to first network output terminals, second network input terminals to any one of the second network output terminals, and operation elements and the network output terminals are connected so as to minimize a constraint strength between the plurality of net...

An integrated circuit includes a functional circuit, a setting memory for storing a setting data item and an input circuit for receiving signals via an input terminal. The input circuit includes a first receiving circuit having first hysteresis and a second receiving circuit having second hysteresis wherein the input circuit connects either the first or the second receiving circuit to the input terminal on the basis of the setting data item in order to receive the signals and to provide the func...

A short-circuit protection circuit for a switching output having a non-self-protected field-effect transistor to whose control electrode a control voltage can be supplied via an input. A series circuit comprising a timer, a switch-off release stage and a switch-off stage is provided at the control electrode of the non-self-protected semiconductor switch.

The present invention provides a novel circuitry comprising a series connection of a plurality of invertor gates, each of which has field effect transistors, wherein at least one of the field effect transistors has a back bias control terminal; and a various bias voltage generator being capable of generating at least one bias voltage and also capable of varying the at least one bias voltage individually, the various bias voltage generator being also electrically connected to the back bias contro...

An adder circuit includes a 4-2 compression circuit in which a NAND signal of a first input signal and a second input signal and an exclusive-OR signal of the first and second signals are produced. When the exclusive-OR output is true, a third signal is output as an intermediate carry-out signal while when the exclusive-OR signal is false, a NOT signal of the NAND signal is output as the intermediate carry-out signal. Therefore, the circuit can be reduced in size by reducing the number of necess...

Several different types of look-up tables are available in the present invention. That is, one look-up table is selected for each m-bit dataword according to the number of consecutive 0's at lower digits, which include a lowermost digit, of the n-bit codeword preceding thereto and the encoding is performed by using the selected look-up table. Furthermore, the bit-pattern at the lower digits, which include a lowermost digit, of a current n-bit codeword is replaced according to the number of conse...

A short-circuit protection circuit senses the output current of an output transistor to provide a control signal to a control transistor. The control transistor, in response to the control signal, varies an input voltage to an internal stage of an amplifier driving the output transistor, so as to cause the output transistor is switched off. A hysteresis resistor is coupled in series with an input terminal of the short circuit protection circuit, so as to prevent transient noise from switching of...

Image data is transmitted from a memory to a CPU (central processing unit). A transmission circuit of the memory receives an 8-bit source parallel signal, makes reference to transmission histories or to transmission predictions to generate a 2-bit coded parallel signal from the source parallel signal, and sends a serial signal as a result of converting the coded parallel signal, together with a flag signal indicative of the presence of an encoding. If the source parallel signal remains unchanged...

An input circuit has an inverter and a differential amplifier, which are respectively connected on an input side to an input and on an output side to an output of the input circuit. The input circuit has two operating modes defined by an activation signal, the differential amplifier being activated and the inverter being deactivated in a first operating mode, and the differential amplifier being deactivated and the inverter being activated in a second operating mode. In this manner, the input ci...