The objective of combinatorial chemical synthesis is the preparation of a very large number of different molecular entities by a randomized process of sequential chemical syntheses. The present invention provides a combinatorial vessel comprising a reaction region and a mixing region, adjacent to each other, which can be used to practice combinatorial chemical synthesis. The reaction region comprises a plurality of reaction cavities, in which a plurality of different chemical reactions may be pe...

In the present invention a method for generating tests for a combinational logic circuit of the PLA type is disclosed. The method is suited to generate tests to determine the input signals, the mid-term output signals of the AND gates, and the output signals, for stuck-at-0 and stuck-at-1 conditions.

The power consumption by a combinational logic circuit having primary input and output terminals is reduced. The constituent gates of the combinational logic are clustered in terms of the operating voltage levels thereof. First, the gates driven with the highest operating voltage are clustered just adjacent to the primary input terminals. Next, the gates driven with the next higher voltage are clustered adjacent to the primary input terminals only through the gates driven with the highest voltag...

A method and apparatus that couple a change input scan chain test pattern with an initialization scan chain test pattern such that a resultant scan chain test pattern is produced, and apply the resultant scan chain test pattern to at least one combinational logic path. In one embodiment, the coupling is achieved by interleaving the change input scan chain test pattern with the initialization scan chain test pattern. In another embodiment, the coupling is achieved by creating a constructed test p...

A combination delay circuit for use in a frequency multiplier comprises a first delay circuit including a plurality of delay lines each having eight segments each effecting a unit delay time t.sub.d, a latch array having 8 latch elements, one element disposed for each delay line, each receiving an output from a corresponding one of delay segments, and second through eighth delay circuits each having a single delay element effecting the unit delay time. The corresponding between the latch element...

A power supply circuit for two automotive headlamps includes a power source supplying electrical power to the headlamps via two fuses, an electrical switch for establishing communication between the headlamps and the power source, a control unit for selectively establishing communication between the headlamps and the power source in series through a single fuse and between the headlamps in parallel and the power source through respective separate fuses, and for blocking communcation between the ...

Constant pins are determined in a combinational circuit by associating an input of a combinational circuit with a first variable and a second variable, with the second variable being the complement of the first variable. For a first logical cell interconnected to such input, a first mathematical representation and a second mathematical representation are computed. The first mathematical representation is a function of the operation of the first logical cell and a function of the first variable, ...

A logic module includes a first and a second two-input multiplexer each having first and second data inputs. Both the first and second multiplexer include a select input, both of which are connected to the output of a two-input logic gate of a first type having first and second data inputs. The inputs to the first and second two-input multiplexers are sourced with data signals from a first group. One input of each of the logic gates is sourced from a data signal of a second group and the other i...

For a system such as a combinational weighing system that requires a large number of parameters to be set for its operation, groups of parameters which frequently assume same sets of values are identified and each of such sets is assigned a reservation number. Memory space for storing values assumed by the parameters can be reduced if these values are grouped by such frequently occurring combinations and the user specifies a single reservation number instead of specifying values of the individua...

A method and apparatus for creating a memory model for use in modeling a physical memory of an electronic circuit design. Memory write operations to the physical memory and memory read operations are modeled in a lookup table. The number of entries in the lookup table is limited by an upper bound representing a total number of memory operations that can occur over a given number of clock cycles.