A data processing system provides the correct weighted combinational function for any unweighted combinational rules applied to a database. The system receives weights to be applied to data attributes, checks for ordering conditions and if necessary re-orders the weights, and produces the correct, unique combinational function that incorporates the user weights into the base combinational rules that otherwise would be applied to retrieve desired data from the database. Thus, the invention provid...

A distributing table construction in a combinatorial weighing apparatus includes a conical main table mounted on a vibrator and slanted at a relatively small angle for distributing and supplying articles to be weighed, such as pieces of cheese or jelly, into a number of radial troughs, and a smaller-diameter conical subtable disposed over the conical main table and connected thereto by a bolt, the conical subtable being slanted at an angle larger than the small angle of the conical main table. T...

Combinational logic circuits are implemented with Inverter Function Logic gates. Such circuits may utilize the logical complement of an input signal in the logical operation performed by the gate without having to use a separate inverter stage or a dual level Cascode arrangement. If such circuits employ the feature of collector dotting, diode clamps are not required. Combinational logic circuits fabricated with Inverter Function Logic utilize a level shifted transistor means in lieu of the stand...

PASS transistors are used to reduce the layout complexity of logic circuits by using PASS transistors connected to pass a first and second input function to an output node in response to selected control signals, thereby to generate a selected output function on the output node. The PASS transistor comprises a transistor capable of passing an input function in response to a control signal applied to the transistor thereby to generate an output function related to the input function. In general, ...

PASS transistors are used to reduce the layout complexity of logic circuits by using PASS transistors connected to pass a first and second input function to an output node in response to selected CONTROL signals, thereby to generate a selected output function on the output node. The PASS transistor comprises a transistor capable of passing an input function in response to a CONTROL signal applied to the transistor thereby to generate an output function related to the input function. In general, ...

PASS transistors are used to reduce the layout complexity of logic circuits by using PASS transistors connected to pass a first and second input function to an output node in response to selected CONTROL signals, thereby to generate a selected output function on the output node. The PASS transistor comprises a transistor capable of passing an input function in response to a CONTROL signal applied to the transistor thereby to generate an output function related to the input function. In general, ...

A combination error detector to detect errors in an InfiniBand packet. The detector includes registers that stores fields of an InfiniBand packet as the packet is being received and comparison logic that, as the fields are stored in the registers, compares the fields with check values and when an error is detected sets a flag corresponding to the error. After the packet has been completely received and all checks have been complete, all of the error flags are prioritized in accordance with the I...

A method and system of latch mapping for performing combinational equivalence checking on a specification and an implementation of a circuit that does not depend on signal names or circuit structure to determine the latch mapping. First, every latch is mapped to every other latch. Then, the resulting mapping is refined until it is semi-inductive. The refinement is performed by randomly producing a state that satisfies the mapping and applying a random input vector to the circuits. The resulting ...

A hardware accelerator includes hardware support for a combinational only cycle and a latch only cycle in a simulation model with a single partition of latches and combinational logic. Preferred embodiments use a special 4-input 1-output function unit in the hardware accelerator in place of the normal latch function that write back the old latch value for combinational only cycles. Other embodiments include hardware support for separate array write disables for arrays and transparent latches dep...

A logic module includes a first and a second two-input multiplexer each having first and second data inputs. Both the first and second multiplexer include a select input, both of which are connected to the output of a two-input logic gate of a first type having first and second data inputs. The inputs to the first and second two-input multiplexers are sourced with data signals from a first group. One input of each of the logic gates is sourced from a data signal of a second group and the other i...