A combinational logic circuit for determining whether an address is inside or outside a range at least partially defined by a control address bit. The logic circuit includes combinational logic connected to an address bit line for receiving the address bit being tested and connected to a control address bit line for receiving the control address bit at least partially defining the range. The combinational logic is configured to produce a signal indicating whether the address bit being tested and...

Speed, size, and power trade-offs of a VLSI combinational circuit are optimized through iterative restructuring. First, timing analysis for the circuit is performed (102) to find the critical path through the circuit (104). Then, a gate is selected from the critical path (106), and a window is contracted around the gate (108). Within the window, alternate structures are constructed (110) and sized (112). The best alternative is substituted into the window (114), and the new circuit is resized (1...

A verification technique which is specifically adapted for formally comparing large combinational circuits with some structural similarities. The approach combines the application of Binary Decision Diagrams (BDDs) with circuit graph hashing, automatic insertion of multiple cut frontiers, and a controlled elimination of false negative verification results caused by the cuts. Multiple BDDs are computed for the internal nets of the circuit, originating from the cut frontiers, and the BDD propagati...

A method and apparatus for creating a memory model for use in modeling a physical memory of an electronic circuit design. Memory write operations to the physical memory and memory read operations are modeled in a lookup table. The number of entries in the lookup table is limited by an upper bound representing a total number of memory operations that can occur over a given number of clock cycles.

A picture element for an electro-luminescent display comprises a substrate, a first intermediate structure disposed above a first area of the substrate, at least one first color type electro-luminescent device disposed above the first intermediate structure, a second intermediate structure disposed above a second area of the substrate, and at least one second color type electro-luminescent device disposed above the second intermediate structure. The second intermediate structure is different fro...

A structure for an array combinational type of windshield wiper comprises an elastic curved strip, a supporting mount, and a plurality of lodging blocks and a plurality of counterweight blocks which are disposed on the elastic strip in an array. This arrangement provides flexibility in matching the length of the array of lodging blocks and counterweight blocks with the length of the elastic curved stripe such that various windshield wipers of different lengths and specifications can be easily pr...

System and software for verifying that a model of an integrated circuit satisfies its specification includes performing a sequence of at least one sequential transformation on a sequential model of the integrated circuit to produce a simplified sequential model of the integrated circuit. Thereafter, the simplified sequential model is unfolded for N time steps to create a combinational representation of the design. A sequence of at least one combinational transformation algorithms is then perform...

An approach that uses a combinatorial approach by adopting natural language processing with the application of Finite State Morphology (FSM) to transform source code into an efficient assembly code. In one example embodiment, this is accomplished by modifying a source code, including multiple instructions, using Lexical Functional Grammar Analysis (LFGA) operation on each instruction as a function of specific Digital Signal Processor architecture. The structure of the modified source code is the...

A system and method for providing error recovery to an asynchronous logic circuit is presented. The asynchronous logic circuit with error recovery may use temporal redundancy to compare the results of an asynchronous computation and initiate error recovery if necessary. Outputs of the asynchronous logic circuit are compared using a plurality of asynchronous register voters. If an asynchronous register voter detects an inconsistent result, the asynchronous register voter clears itself. A majority...

Test pattern generation is performed for a sequential circuit by first separating the circuit into overlapping pipelines by controlling corresponding clocks for one or more registers of the circuit so as to break feedback loops of the circuit, and then processing each of the pipelines separately in order to determine if particular target faults are detectable in the pipelines. Independent clocks may be provided for each of a number of registers of the circuit in order to facilitate the breaking ...