A system and method for hardening an asynchronous combinational logic circuit against Single Event Upset (SEU) is presented. The asynchronous combinational logic circuit is located between two asynchronous registers. A fault detector is used to detect a fault at an output of the asynchronous combinational logic circuit caused by SEU. If the fault detector detects a fault, a first asynchronous register is prevented from clearing stored data and a second asynchronous register is prevented from loa...

A method and apparatus that couple a change input scan chain test pattern with an initialization scan chain test pattern such that a resultant scan chain test pattern is produced, and apply the resultant scan chain test pattern to at least one combinational logic path. In one embodiment, the coupling is achieved by interleaving the change input scan chain test pattern with the initialization scan chain test pattern. In another embodiment, the coupling is achieved by creating a constructed test p...

A method for filtering events in a computing system using a low power device, Personal Data Assistant is provided. The filtering is done without the involvement of the processor of the computing system. The filtering of events include authorizing requests from wireless devices before the processor's resources are utilized. In a mobile computing system, pre filtering by low power device reduces the amount of time the processor needs to be active. The personal digital assistant also provides certa...

An apparatus for and method of eliminating single event upsets (or SEU) in combinational logic are used to prevent error propagation as a result of cosmic particle strikes to the combinational logic. The apparatus preferably includes a combinational logic block electrically coupled to a delay element, a latch and an output buffer. In operation, a signal from the combinational logic is electrically coupled to a first input of the latch. In addition, the signal is routed through the delay element ...

Control signals for phase-delay rectifiers, which require a variable firing angle that ranges from 0.degree. to 180.degree., are derived from line-to-line 3-phase signals (.phi.A, .phi.B, .phi.C) and both positive and negative firing angle control signals (+.alpha. and -.alpha.) which are generated by comparing (at 20) current command and actual current (sensed at 16). Line-to-line phases are transformed (32) into line-to-neutral phases and integrated (at 34) to produce 90.degree. phase delayed ...

A wired combinational logic arrangement responsive to N binary signal sources includes N circuits, one for each source. The circuits drive a common output terminal. Each circuit includes first and second devices for pulling the common terminal to first and second different voltages during successive abutting activation periods. The first device supplies a current to the common terminal that is considerably greater than the current supplied to the common terminal by the second device. The arrange...

A logic module includes first and second multiplexers each having two data inputs and a select input. Both select inputs are connected to the output of a two-input logic gate of a first type. The inputs to the first and second multiplexers comprise data signals from a first group. One input of each logic gate comprises a data signal of a second group and the other input of each logic gate comprises a data signal of a third group. A third multiplexer has first and second data inputs connected the...

Combinational weighing by ranks is carried out by supplying articles of different weights to a plurality of weighing devices one at a time, measuring individual weights of these articles by the weighing devices, classifying the weighed articles individually into ranks according to their measured weights, and carrying out combinational weighing only on those of the weighed articles in a same rank. The combinational weighing is carried out preferentially on the articles in the most populated rank....

A logic module 400 for use in a field programmable gate array 100 can be selectively reconfigured to perform over 1800 Boolean combinational functions on each output 431-432, to operate as a full adder with sum and carry outputs, or to form the sequential function of a D-latch or a D-flipflop. The logic module has ten input terminals 411-418, 421-422 and two output terminals 431-432. The logic module is comprised of two-input multiplexors 500 and 600 which are used to form both the combinational...

An encoder system and technique is disclosed for providing greater resolution for position indications. The encoder includes multiple small absolute encoders coupled through a fixed gear ratio to provide an increase in the number of positions which may be absolutely resolved by the encoder without a significant increase in the size of the encoder. The resulting configuration produces a size which is the sum of the individual sizes of the multiple encoders but produces a resolution which is propo...