An oscillator for very high microwave or millimeterwave frequencies employs a pair of negative-resistance semiconductive devices, each mounted in its own resonant cavity. The two cavities are coupled together by an iris in their common wall. An output waveguide is coupled symmetrically to both sides of the common wall to load both cavities equally. An adjustable mode-control element projects into the cavity to the near vicinity of one of the devices to induce the oscillator to start in the desir...

A method and apparatus for improved detection of reflected seismic energy through detection of air pressure variations in air above an air/earth surface interface. One form of apparatus suitable for detection in air of seismic energy waves emanating from beneath the earth surface consists of supporting a collecting reflecting member over a designated earth surface site and detecting air pressure variations at a focal point within the reflector member; and, thereafter, transmitting or conducting ...

An electrical connector for applications where reliability and safety are needed uses transformer couplings made in two separable sections. Upon clamping together the surrounding metal housing halves, each inductively coupled pair of transformer windings is enclosed by the associated cup-type ferrite magnetic core to minimize undesired interference and result in good magnetic coupling.

A high-volume, heavy-duty, magnetically-coupled centrifugal pump having flow-dividing duct configurations directing the influx to opposite sides of the impeller as the result of assembly of mating body sections defining a multi-chambered pump body and including major partitioning web and cavity configurations with cooperative plate means affording certain inflow-chamber, shaft-support, and turbulence-suppressing chamber configurations operative to diminish turbulence volume and also block transf...

A high speed multiplier array implemented with a current switch emitter follower logic gate employs an inverted carry signal internal to the array. External carry signals received by the array are first inverted for internal processing. This implementation eliminates the necessity of employing a buffer gate between subarray integrated circuit chips or cells and thus decreases propagation delays in the overall array.

A first charge storage electrode (21) has a first row (21b) of teeth interdigitated with a second row (22b) of teeth of a second charge storage electrode (22). The second storage electrode (22) has a third row (22c) of teeth interdigitated with a fourth row (23b) of teeth of a third charge storage electrode (23). The first and third rows (21b and 22c) overlie one group (11b) of a series of parallel conduction channels while the second and fourth rows (22b and 23b) overlie another group (11a) of ...

An emitter-coupled logic circuit, including first to fourth n-p-n transistors, the first transistor having its base connected to a first input signal source and its collector connected to a first supply voltage source, the second transistor having its base connected to a second input signal source and its collector connected to the first supply voltage source, the first and second transistors having their emitters connected to a second supply voltage source via a constant current source, an n-p-...

A central processing unit includes an instruction decoder (1), an operand address computation unit (2), an operand pre-fetch unit (3), a control information buffer (5), an arithmetic unit (4), an instruction fetch unit (6), a chip bus (7), and a bus controller (8). A process relating to the fetch of a memory operand is independent from main pipeline process having an instruction fetching stage, an instruction decoding stage, and an instruction execution stage. As a result, control information (1...

A base-coupled logic gate is characterized by input Schottky diodes that are directly formed on the base region of the switching transistor for the gate. A logic of this type provides flexible circuit arrangements and savings in a required area, while achieving very high speeds. As a result of the savings in area, the buried layer capacitance of the gate is also reduced, which facilitates the high-speed operation of the circuit.

An amplifier has first and second differential amplifier circuits connected in parallel for improving the distortion ratio characteristic and the like, with the first differential amplifier circuit including first and second transistors connected in common at respective emitters to a first constant current source, and the second differential amplifier circuit including third and fourth transistors connected in common at respective emitters to a second constant current source. The first different...