A method of compressing digital image or image-like pixel data. The method comprises carrying out the following steps on small blocks of pixels: a) determining the differences between digital values of adjacent pixels in the block to define respective link weights; b) determining a tree connecting all the pixels in the block such that the sum of the link weights in the tree is a minimum; c) dividing the tree into segments by removing links with weights greater than a threshold value, so dividing...

A data receiver includes first and second mixers mixing an input RF signal and a local oscillator signal and generating first and second quadrature baseband-frequency output signals. A phase shifter shifts a phase of the first baseband-frequency output signal by 90 degrees. A third mixer mixes an output signal from the phase shifter and the first baseband-frequency output signal. A fourth mixer mixes the first and second baseband-frequency output signals. A demodulator performs data demodulation...

A technique for achieving read-time animation in bit-map data displays in apparatus having a display memory in which digital codes are stored to give the color and/or luminance of each pixel of the display and the display memory is accessed repeatedly in a recurrent display scan cycle to read-out the digital codes to produce the display. The time available for modifying the contents of the display memory to achieve animation of an object against a fixed background is very small and access to the...

A LAN or other data network includes at least first and second repeater units for receiving data signals and repeating them to other parts of the data network and a transceiver unit for transmitting and receiving data which is connected to the first repeater unit by a primary data link and to the second repeater unit by a secondary data link. The primary data link comprises a primary transmit line for transmitting data from the transceiver unit to the first repeater unit and a primary receive li...

The efficiency of a processor in which a packet is stored in a receiver buffer, processed in a central processing unit, and sent out via a transmitter buffer, is low. According to the invention, data is transferred to a high-speed memory via the receiver memory. When the high-speed memory is filled with data, the data is processed by the CPU, and the packet is transmitted from the high-speed memory via the transmitter memory. A competition control section is provided to control data accesses in ...

A data processor which has instructions of operation and comparison when including the signed binary number represented by complement on 2 as the object and has a flag correctly representing the result of the operation as positive or negative regardless of whether or not overflow occurs so as to correlate the arithmetic operation close with a status flag change, thereby facilitating mathematical interpretation of the result of the operation.

A method of securing data recorded on a data support and a device for performing the method are disclosed. In addition to the basic information contained in the data recorded on the data support, for generating an additional security code, selected individual properties of the recorded data are used which differ from each other as regards their physical and/or chemical properties. In one embodiment, individual characters imprinted on the data support are used which differ from each other with re...

A method of modifying a digital representation of an image in which digital data defines the content of pixels of the image. The method comprises a) determining whether a predetermined degree of compression can be achieved if data defining a block of pixels is compressed by applying a predetermined compression algorithm; and, if not, b) discarding a portion of the data in the block, and repeating steps a and b on the most recently modified block until the predetermined degree of compression is a...

A microprocessor has a register in which attributive data corresponding to a memory to be coupled to the microprocessor is written, and a control circuit which controls address signals to be supplied to the memory in accordance with the attributive data. The attributive data is composed of range data for discriminating ranges of address data supplied to an address bus, system data indicative of addressing systems of the memories corresponding to the respective address ranges, and bit number data...

An algorithm or technique for compacting (and expanding) digital data is disclosed in which the data is broken up into words or lexemes. The words are entered into a push-down list as they are received and, if already on the list, a list location identifier is transmitted and the word moved to the top of the list. The last word on the list falls off the list when a new word is entered at the top and thereafter is treated as a new word. The data expander maintains identical lists and substitutes ...