Titanium boride (TiB.sub.x), zirconium boride (ZrB.sub.x) and hafnium boride (HfB.sub.x) barriers and electrodes for cell dielectrics for integrated circuits, particularly for DRAM cell capacitors. The barriers protect cell dielectrics from diffusion and other interaction with surrounding materials during subsequent thermal processing.

The specification describes silicon MOS devices with gate dielectrics having the composition Ta.sub.1-x Al.sub.x O.sub.y, where x is 0.03-0.7 and y is 1.5-3, Ta.sub.1-x Si.sub.x O.sub.y, where x is 0.05-0.15, and y is 1.5-3, and Ta.sub.1-x-z Al.sub.x Si.sub.z O.sub.y, where 0.7>x+z>0.05, z<0.15 and y is 1.5-3. By comparison with the standard SiO.sub.2 gate dielectric material, these materials provide improved dielectric properties and also remain essentially amorphous to high temperatur...

A semiconductor device and a method of making the semiconductor device having a composite dielectric layer including steps of providing a semiconductor substrate; depositing on the semiconductor substrate alternating sub-layers of a high-K dielectric material and a dielectric precursor material to form a composite layer having at least two sub-layers of at least one of the high-K dielectric material and the dielectric precursor material. The semiconductor device may be subjected to annealing at ...

The present invention provides a low-k dielectric etching process with high etching selectivities with respect to adjacent layers of other materials, such as an overlying photoresist mask and an underlying barrier/liner layer. The process comprises the step of exposing a portion of the low-k dielectric layer to a plasma of a process gas that includes a fluorocarbon gas having a relatively low fluorine to carbon ratio, a nitrogen-containing gas, and an inert gas, wherein a volumetric flow ratio o...

An embodiment of the invention is a method of manufacturing a semiconductor wafer. The method includes depositing spin-on-glass material over the semiconductor wafer (step 208), modifying a top surface of the spin-on glass material to form a SiO.sub.2 layer (step 210), applying a vapor prime (step 212), forming a photoresist layer over the spin-on-glass material (step 214), patterning the photoresist layer (step 214), and then etching the semiconductor wafer (step 216). Another embodiment of the...

Capacitors 10, 20, 40, 50, 70, 80) having a fluid dielectric material that is transported or undergoes a phase change are disclosed. The dielectric medium change results in a change in the total dielectric constant of the material between the electrodes (12, 14, 72, 74, 81, 82), thus changing the capacitance of the capacitors. Transporting or phase changing the dielectric fluids into and out of a the electric field of the capacitor, changes the effective dielectric constant and the capacitance o...

The present disclosure pertains to a method for plasma etching of low k materials, particularly polymeric-based low k materials. Preferably the polymeric-based materials are organic-based materials. The method employs an etchant plasma where the major etchant species are generated from a halogen other than fluorine and oxygen. The preferred halogen is chlorine. The volumetric (flow rate) ratio of the halogen:oxygen in the plasma source gas ranges from about 1:20 to about 20:1. The atomic ratio o...

The specification describes silicon MOS devices with gate dielectrics having the composition Ta.sub.1-x Al.sub.x O.sub.y, where x is 0.03-0.7 and y is 1.5-3, Ta.sub.1-x Si.sub.x O.sub.y, where x is 0.05-0.15, and y is 1.5-3, and Ta.sub.1-x-z Al.sub.x Si.sub.z O.sub.y, where 0.7>x+z>0.05, z<0.15 and y is 1.5-3. By comparison with the standard SiO.sub.2 gate dielectric material, these materials provide improved dielectric properties and also remain essentially amorphous to high temperatur...

An improved method for forming inter-metal dielectrics (IMD) over a semiconductor substrate is provided, wherein a conductive line is formed thereon. A first dielectric layer is formed over the conductive line. A second dielectric layer is formed on the first dielectric layer by a spin-on glass method. A curing treatment with an electron beam having a low energy and a high dosage is performed to cure an upper portion of the second dielectric layer so that a cured third dielectric layer is formed...

Titanium boride (TiB.sub.x), zirconium boride (ZrB.sub.x) and hafnium boride (HfB.sub.x) barriers and electrodes for cell dielectrics for integrated circuits, particularly for DRAM cell capacitors. The barriers protect cell dielectrics from diffusion and other interaction with surrounding materials during subsequent thermal processing.