
A data pattern generator in which the address generation of a program counter (11) is controlled in accordance with an operation code and an operand read out of an instruction memory (12'). An address/data pattern is generated in response to an address/data computing instruction read out of the instruction memory (12'). Random logic patterns for testing a logic circuit are prestored in a data buffer memory (18) and are read out therefrom using an address created by an address pointer (19). The a...











