A memory capable of easily setting a reference potential and correctly determining data is provided. This memory comprises a ferroelectric capacitor holding data, and a driving line and a data line linked with the ferroelectric capacitor. The memory applies a voltage pulse to the ferroelectric capacitor through the driving line when reading the data thereby generating a negative potential on the data line if the ferroelectric capacitor holds first data, or generating a positive potential on the ...

A memory capable of effectively reducing the chip size not only by sharing a read/write circuit but also by reducing a memory cell size is provided. This memory comprises a first memory cell array having a plurality of first memory cells, a second memory cell array having a plurality of second memory cells different in type from the first memory cells and a selection control circuit provided separately from the first memory cell array and the second memory cell array for controlling selection of...

A memory allowing reduction of the period of an external access operation is provided. This memory comprises an access control portion performing an internal access operation on the basis of an external access operation, a refresh control portion performing a refresh operation and a refresh division control portion dividing the refresh operation into a read operation RFRD and rewrite operations RFRS1 and RFRS2. The memory performs the read operation RFRD and the rewrite operations RFRS1 and RFRS...

A memory capable of suppressing reduction of a reading voltage in data reading regardless of dispersion in a manufacturing process is provided. This memory comprises charge storage means, a first field-effect transistor and data determination means. The memory sets a voltage between a control terminal and a remaining first terminal of the first field-effect transistor to a threshold voltage for bringing the first field-effect transistor into an OFF-state in the vicinity of a boundary state betwe...

A memory capable of performing a refresh operation uncompetitively with an internal access operation also when an external access operation is non-cyclically performed is obtained. This memory comprises an external access detection portion detecting an external access operation, an access control portion performing an internal access operation on the basis of the external access operation and a refresh determination portion determining whether or not to perform a refresh operation on the basis o...

A memory capable of suppressing disturbance causing disappearance of data in a nonselected memory cell is provided. This memory comprises a memory cell array including a bit line, a word line arranged to intersect with the bit line and memory cells connected between the bit line and the word line, for accessing a selected memory cell thereby deteriorating a remanent polarization in an arbitrary memory cell and thereafter performing recovery for recovering all memory cells to remanent polarizatio...

This memory comprises a bit line, a first word line and a second word line arranged to intersect with the bit line while holding the bit line therebetween and a first ferroelectric film and a second ferroelectric film, having capacitances different from each other, arranged between the bit line and the first word line and between the bit line and the second word line respectively at least on a region where the bit line and the first and second word lines intersect with each other. The bit line, ...

A memory and control circuit for the memory with a memory including a first memory plane area having a plurality of memory cells arranged in a matrix array and a plurality of second memory plane areas each having a plurality of nonvolatile memory cells arranged in a matrix array, the first memory plane area being arranged in a superposed relation to the second memory plane area and the memory cell in the first memory plane area being connected to the corresponding memory cell in the second memor...

A memory cell of the bistable type which is capable of being read from, written into or having its contents interrogated is disclosed herein. The memory cell performs these various operations through a minimal number of external line connections which include a word line and an interrogate line. The memory cell is capable of being arrayed in such a manner as to allow for separate operations on any number of individual cells. The memory cell is also configured in such a way as to allow for a mini...

Piezoelectric photosensitive semiconductor crystals or semi-insulators are employed either to store or to process high frequency signals. Storage is accomplished in the crystal by a stable pattern of trapped electrons produced by the interference between two radio-frequency input signal pulses. The latter are applied successively to the crystal, after an initial illumination, causing ultrasonic waves to be generated. The ultrasonic wave of the first pulse, together with the electric field of the...