An electronic private automatic branch exchange includes a digit decoder, a hold register, a line selector, a plurality of junctors and a junctor memory, the junctor memory having a plurality of storage locations each capable of storing data relating to line circuits to be connected to a junctor assigned to the particular storage location. A data select circuit is responsive to a control signal derived from a logic control circuit which receives common control command to selectively gate data fr...

A memory circuit is disclosed in which a first capacitor is connected in parallel between the gate and common electrodes of an insulated gate field effect transistor, the gate electrode thereof is connected through a first switching element to one end of a second capacitor, the other end of the second capacitor is connected to the common electrode of the insulated gate field effect transistor, a second switching element is connected in series between the connection point of the first switching e...

An associative memory comprising a bistable circuit including a couple of multi-emitter transistors each having at least two emitters, the base and collector of one of said transistors being electrically connected respectively with the collector and base of the other transistor, ternary level voltages being applied to the emitters of each of said transistors as required thereby performing association.

Integrated solid-state memory in the form of an array, including row selection members, matching amplifiers and bit selection members which are fabricated on the same integrated circuit. The bit selection members include a shift register which, under the control of a selection instruction and a clock signal, sequentially selects a sequence of at least one bit location within a selected array row, the first bit location of the sequence being adapted to be set at random.

A memory device for automatic switching control systems using pulse patterns for the switching control. The working pulse pattern and the test pulse pattern are fed to the input of a shift register which has one more register stage than the number of clock pulses per pulse pattern. The clock pulse signal and an erase signal pattern, which is present as required are also fed to the shift register. A logic circuit arrangement is connected to the shift register to detect the presence of a working p...

An associative memory comprises address memory modules, detectors, and interrogation register and interrogation converters, the flip-flops of the interrogation register being divided into groups, and the inputs of each interrogation converter being coupled electrically to the outputs of a respective group of the flip-flops in the interrogation register, while the outputs of each interrogation converter are coupled electrically to the address buses of respective address memory modules. The interr...

A memory cell utilizing first and second cross-coupled CMOS inverters connected to a digit line. During a read command, one inverter is disconnected from the input node of the other inverter to prevent loss of the stored information.

A memory circuit employing insulated-gate field-effect transistors includes a first circuit for generating a signal upon the completion of one of the circuit functions involved in the operation of the memory circuit. That signal is applied to a second circuit which thereupon produces a timing signal that is used to control a second circuit function of the memory circuit.

A memory mechanism for controlling incremental change of informations in a plurality of information systems to be indicated successively in turn. The mechanism comprises actuation means adapted to be actuated in response to an input signal each time said actuation means receives such a signal, a first memory wheel operated by said actuation means to incrementally change the informations in the first system of said plurality of informations systems and having an intermittent transmission means, a...

A memory watch provided with a rotatable sound-record carrier and an associated electro-acoustic transducer for alternate recording and reproduction has a spring mechanism adapted to store sufficient mechanical energy for driving the carrier through one or more cycles for reproduction alone or for recording and subsequent playback of the recorded message at the command of the user or automatically at a preset time. Recording is blocked unless sufficient energy is stored to enable subsequent play...