Between the memory and the word register of a computer are interposed switching means to permit the recording into or reading out of supplementary memory elements which are used whenever a normal memory element associated with word groups in the memory becomes faulty so that the memory can still be used while repairs are being performed.

A semiconductor memory including a matrix array of storage cells employs read and write word lines oriented along one matrix axis, and common digit lines disposed about the other matrix axis. Each storage cell comprises three interconnected read, write and information retaining insulated gate field effect transistors, information being preserved via stray capacitance at the gate of the information preserving transistor. In accordance with varying aspects of the present invention, information is ...

A triggered neon lamp memory circuit selectively produces control voltages for an electrically tuned receiver. Each stage comprises a neon lamp and a control voltage potentiometer in series with a common source of sustaining potential. In one embodiment, when the neon lamp of a given stage is triggered by manually actuating a touch contact, a series transistor is turned on to effectively couple a fixed voltage to the potentiometer. When the neon lamp turns off, the transistor turns off to remove...

A memory element which is an improved version of the known FAMOS (floating avalanche-injection metal-oxide-silicon) memory elements in that memory erasure is effected electrically. The structure of the known FAMOS memory elements is modified by having at least one diffused region in the silicon substrate which is isolated from the elements gate and drain electrodes, which is of opposite conductivity type to the substrate, and which is situated adjacent to the channel region between the gate and ...

A memory device and a method for selectively controlling the processing of articles in an automated machine performing a sequence of processing steps on the articles as they are moved through successive work stations on the machine. A wheel carries a number of uniformly spaced pins around its circumference, and is indexed in unison with the processing machine, each article being associated with a corresponding pin for the sequence of processing steps. A pin is moved to a new position with respec...

A memory device is disclosed. The memory device is comprised of a plurality of shift registers and a plurality of majority voters. The outputs of each of said shift registers are connected to the inputs of each of said majority voters.

A memory system for simultaneously accessing a memory from a large number of sources includes a cyclic memory from which stored information is continuously read by a plurality of read means and temporarily entered into comparison registers, input registers receive and temporarily store at least one of the coded digits on said memory, and comparators generate a signal upon the existence of a coincidence between a coded digit momentarily in said comparator register and a coded digit temporarily st...

In a dynamic memory circuit which utilizes a periodic refreshing cycle, a clamping signal is provided which prevents an incoming access signal from interrupting the refreshing cycle during a period of the cycle when the stored information in the memory circuit could be destroyed as a result of such interruption.

Disclosed is a memory system for storing digital data; the memory system of the type which may be implemented, for instance, in an electronic microprocessor or calculator system. The memory comprises an array of transistor memory cells arranged in columns and rows. Column conductors are provided for supplying digital information to each column of such cells and row conductors are provided for enabling each row of cells to store digital information being received on the column conductors. A commu...

A high capacity associative read/write memory is provided which includes storage means which can be read from or written into and having memory units of equal capacity each containing an equal and predetermined number of levels. Addressing means are coupled to the memory for addressing the data locations in the memory. A first comparator compares the content of the memory addressed (the data descriptor word) with the words read from the associative memory and a second comparator compares the con...