A semiconductor memory has at least one V-MOS transistor which includes a trench and a storage capacitor. A semiconductor substrate is doped with concentration centers of a first conductivity type and has a buried layer which is doped with concentration centers of a second conductivity type opposite to the first conductivity type. At least two additional layers are divided by the trench and have alternately differing conductivity types, the two additional layers and the buried layer being produc...

An improved READ/WRITE circuit for a memory array of cells arranged in rows and columns, where each cell is coupled to a bit line via the conduction path of a single gating transistor which conducts in the source follower mode for one binary condition. The circuit includes a voltage multiplying circuit having an output at which is selectively produced either a read voltage, or a write voltage of significantly greater amplitude than the read voltage. The output of the voltage multiplying circuit ...

An improved associative memory employs plural separately addressable memories, e.g., random access memories (RAMs), which may be written into, or read from in conventional fashion. In a recognition mode, information is read from differing memory locations, and compared with an operand supplied on a data bus by a central processing unit (CPU), comparator apparatus being common for an array of storage locations. The comparison results, determined in accordance with a CPU-specified criterion, are t...

A plurality of memory cells are connected to first and second data lines, and a circuit for applying a precharge voltage and a dummy cell are connected to each of first and second input lines which are connected to input terminal of a differential amplifier for detecting information of the memory cells. The first and second data lines are connected to the first and second input lines through first and second switching elements, respectively. When the stored signal of one memory cell connected to...

An optoelectronic memory comprising the following elements placed one after another in succession downstream the original beam from the source of electromagnetic radiation: a means for scanning the original beam, which is electrically connected to an address register, a means for splitting the original beam into m beams forming a scan pattern and a focusing lens. The focusing lens is followed by n beam splitters whose number along each beam direction is equal. The memory also comprises .vertline...

A memory transistor in which a photovoltaic-ferroelectric element is conned between the gate and source of a field effect transistor. The element stores a remanent polarization in a direction corresponding to the polarity of a voltage to be applied to the transistor, and when the element is illuminated the voltage is generated and is applied. A restorable cross-coupled flip-flop in which memory information is stored in a pair of photovoltaic-ferroelectric elements. If power is lost, the elements...

Disclosed is the addition of a capacitor circuit for augumenting the voltages at predetermined points in a sense amplifying circuit, in order to ensure a satisfactory refreshing of memory cells, since, if the potentials at the connecting points between a sense amplifying circuit and bit lines fall below a predetermined value when the sense amplifying circuit is caused to operate, it is difficult to achieve a complete refreshing of the memory cells.

A memory stable against variation of an external supply voltage is disclosed. The memory comprises a plurality of memory cells, each of memory cells including an insulated-gate field-effect transistor having a gate coupled to a word line, a source and a drain, one of the source and drain being coupled to a digit line, and an information storage capacitor having a first electrode coupled to the other of the source and drain of the transistor and a second electrode, and means for biasing the secon...

A memory circuit comprising a memory cell for storing information, constituted of semiconductor circuit elements and the associated circuit elements, and a control input section provided on the input side of the memory cell for controlling the memory cell, constituted of transistor means and current control means, wherein one of ON and OFF states is selected and also held in accordance with more than two logic input signals supplied to the control input section and no power is consumed to hold t...

A memory pack is provided having a random access memory connected between a positive power source terminal and a ground terminal, an addressing terminal coupled with the random access memory, and a data input/output terminal coupled with the random access memory. The memory pack further includes an LED energizing terminal, a light emission element which is connected between the LED energizing terminal and a positive power source terminal, the LED being lit by an energizing signal applied to the ...