A memory device operable at high speed is disclosed. The device comprises selection means coupled to word lines for selecting one of them detection means for detecting a signal appearing in the selected word line, and word line drive means responsive to an output of the detection means for supplying the selected word line with a voltage capable introducing a selection level in it independent on the selection means.

A two-clock multi-address input dynamic random access memory provided with an internal refresh function for refreshing memory cells without receiving refresh address information from the outside is disclosed. The memory characteristically comprises a terminal for receiving a refresh control signal, refresh address means for designating a row address to be refreshed, means for producing confirmation signal when a reset precharge of a circuit relating to a refresh operation is completed, means for...

A plurality of single transistor memory cells with electrically charged capacitors and two similar dummy memory cells are electrically coupled in symmetric relationship to a sense amplifier for each row of the disclosed memory circuit. An address signal selects a word line connected to the memory cell on one side of the amplifier and a dummy word line connected to the dummy memory cell on its other side and applies a word signal to the selected word lines, in order to read out electric charges o...

A memory system is shown in which communication to and from memory cells is effected by optical beams. Memory cells are shown employing elements with negative resistance and operating in either of two stable modes. Other memory cells are shown employing subharmonic oscillators operating in either of two phase relationships. The memory cells and systems permit extremely fast operation.

A random access type semiconductor memory comprises a pair of data line halves arranged in parallel, a plurality of word lines orthogonal to the data line halves, a multiplicity of memory cells, each of which is arranged at either one of the cross points between the data line halves and each of the word lines, a differential amplifier to which signals on the data line halves are differentially applied, and a main amplifier to which output signals on the data line halves are differentially applie...

A memory array includes row conductors which have to be charged to a first level prior to each read-out cycle. During a read-out cycle the row conductors may or may not be discharged to a second level depending on whether a "1" or a "0" is stored at selected bit locations. The memory array also includes "dummy" row conductors which are discharged to the second level each time the contents of the array are read out. Means are provided for charging the row conductors including the "dummy" row cond...

A READ ONLY memory is disclosed wherein the bits of a given word are separately stored in a number of individual storage arrays. The individual storage arrays each contain a plurality of addressable bit storage locations. These bit storage locations are first accessed and thereafter sensed in response to a given address. The accessing and sensing is implemented by current mode logic in a manner which effectively develops and thereafter utilizes various current paths.

The invention relates to a plate of magnetic material wherein magnetic domains can be formed and driven along guide structures consisting of discrete elements of magnetizable material, for example, vapor-deposited permalloy. The plate is used as a memory, a number of mainly parallel extending input structures forming paths for the domains between relevant outputs of the memory and relevant inputs of a decoding device. The decoding device comprises delay elements which can each be activated by a ...

A memory circuit is comprised of a memory cell of PNPN- equivalent 4-layer construction, a selective input circuit composed of a pair of an NPN transistor and a PNP transistor, and a read-out circuit for reading the information stored in the memory cell. The emitters of the transistors included in the selective input circuit are connected to one of the selective input terminals, the bases thereof to the other selective input terminal, the collector of one of the transistors to the write input te...

A memory system is shown in which communication to and from memory cells is effected by optical beams. Memory cells are shown employing elements with negative resistance and operating in either of two stable modes. Other memory cells are shown employing subharmonic oscillators operating in either of two phase relationships. The memory cells and systems permit extremely fast operation.