A semiconductor memory comprises means for forcing the potential on one data line to which no writing means is connected to be set to a certain level after data have been read from a memory cell, and means for setting the level of the one data line cooperating with another data line supplied with a voltage corresponding to data to be written and a sense amplifier in order to restore the one data line set to the certain level to the voltage corresponding to the data to be written. This allows the...

A semiconductor memory has storage cells composed of MOS selector transistors operated by a drive line and storage capacitors connected to selector transistors. The selector transistors are constructed in accordance with the V-MOS technique. A semiconductor substrate is highly doped with atoms of one conductivity type and carries a buried layer highly doped with atoms of the opposite conductivity type. An epitaxial layer, weakly doped with atoms of the one conductivity type is carried over the b...

A memory circuit including one-transistor-per-bit memory cells arranged in a matrix array of m and n columns, one capacitor, and n differential amplifiers associated with the n respective column. The memory array is divided into first and second row groups and each differential amplifier has a first input terminal connected to memory cells belonging to the first row group and associated with one of the n columns and a second input terminal connected to memory cells associated with the second row...

Transistor memory cells which may be operated in both the erasable "read only" and the "random access" modes. Each cell includes a plurality of MOS transistors interconnected to permit random access storage and at least two MNOS transistors. The latter may be set, one to one threshold level and the other to a second threshold level to represent read only storage of a logic 1, and the threshold levels may be reversed to represent read only storage of a logic 0. The MOS transistors may be randomly...

In a character recognition system lines of data are stored in a line memory via a series of multiplexers. The data can originate in a controller for the system, a character reading station or other sub-systems, and is supplied to the line memory over a controller bus, a transport bus and a line memory bus, respectively. Although stored in line form, two-dimensional sub-arrays of the data in various configurations can be accessed directly by the other sub-systems of the recognition system via the...

An integrated circuit memory array having a plurality of memory cells including two cross-coupled transistors of one conductivity type, load transistors of the other conductivity type, and a bit line, connected to the base region of one of the cross-coupled transistors through a bit line transistor. The array features a common node, directly interconnecting all of the base regions of the load transistors and the emitter regions of the cross-coupled transistors, for each of the memory cells; and ...

This application discloses an associative memory designed to perform search and logical operations on attributive information presented in the form of multi-digit associative words or in the form of sets consisting of a given number of binary associative indications. The associative memory comprises an input register, an interrogation register, groups of coincidence circuits, groups of OR circuits, a mask register, an operation decoder and a data storage unit. The input register, the interrogati...

A memory device is disclosed which has a memory portion comprising a plurality of major memory blocks, each composed of a plurality of minor memory blocks which, in turn, are respectively composed of a plurality of memory cells. Information as to whether each of the minor memory blocks making up each of the major memory blocks includes defective memory cells or not is registered and when an address corresponding to any one of the major memory blocks is selected, a predetermined number of minor m...

An associative memory includes storage units each of which includes an address storage module and an interrogation decoder connected thereto by address buses; an interrogation register having flip-flops connected to the inputs of respective interrogation decoders; detectors connected to the storage units by digit buses; a complementary interrogation decoder to drive respective detectors; a complementary interrogation register to receive and store the complementary interrogation code represented ...

A memory system for analogue data includes a plurality of semiconductor charge device shift registers integrated on a semiconducor substrate. In one embodiment analogue data is serially inputed into a charge-coupled device (CCD) shift register. The serial data is converted to parallel and propagates at a substantially slower speed through a plurality of shift registers. A parallel-to-serial conversion provides a serial readout of the data. The serial-parallel-serial arrangement of the memory sig...