A triggered neon lamp memory circuit selectively produces control voltages for an electrically controlled rado wave receiver. Each stage comprises a neon lamp, a transistor and a control voltage potentiometer coupled in series between a common source of sustaining potential and a point of reference potential. When the neon lamp of a given stage is triggered, the associated transistor is turned on to effectively couple a fixed voltage to the control voltage potentiometer. When the neon lamp turns...

An integrated semiconductor memory with storage elements in a circuit employing a flip flop with field-effect selective transistors and with an arrangement based on the two or multiple coincidence principle, with corresponding control lines.

An information support for a magnetic store provides storage locations made of a storage material of the formula Mn.sub.3 Rh N.sub.x in which x has a value from 0.5 to 0.95 and is preferably in the region of 0.8. The storage material may be deposited as a thin layer or at discrete locations on a substrate such as glass or may be uniformly dispersed as fine particles within a matrix of plastics material forming a thin sheet. The storage material assumes a ferromagnetic state on being heated from ...

A switched impedance element, presenting a high or a low impedance value in response to whether or not an address voltage is applied thereto, is connected with each collector of a pair of transistors which are mutually coupled together in such a manner that the collector and the base of one transistor are connected with the base and the collector of the other transistor, respectively, to thereby form a memory cell. A pair of digit lines are connected with the emitters of the pair of transistors ...

A Search memory organization using as the designator words, which words are the words that are stored in the Search memory and that are compared to the one search word held in the search register, words that are generated from blocks of data words is disclosed. Each of the (block) designator words includes two portions: a first common portion that includes the binary data that are common to all the data words of the block; and, a second word portion that includes the binary data that are not com...

A memory board having a column of items listed on its face and having an individual rotary indicator or pointer positioned abreast of each item for rotary movement between angular positions in which each pointer may either be angularly positioned to designate its associated item or else placed in an inoperative position. The board is formed with a rearwardly opening groove which is bridged by a plurality of relatively spaced apart bearing strips defining internal bearing surfaces disposed on a c...

A semiconductor memory comprising semiconductor elements organized into a plurality of sub-systems individually provided with respective power supply switches each actuated in synchronism with or in response to the select signal to the corresponding sub-system, whereby a predetermined amount of power is supplied only to the selected sub-system while the remaining sub-systems receive no power or just sufficient power to maintain their memory content.

A low power consuming semiconductor memory in which a pair of input/output terminals of a flip-flop are connected with the bases of a pair of transistors the collectors of which are connected to a pair of digit lines. The emitters of the transistors are connected in common with a constant current source through a current switching type semiconductor switching circuit which is adapted to be closed or opened in response to application or non-application thereto of an address signal, so that the fl...

An electronic memory cell consists of a bistable and three access paths. Two of the access paths control the state of the bistable. Connected between the two access paths controlling the state of the bistable and the third access path is a M.O.S. transistor whose impedance varies in dependence upon the state of the bistable.

A core memory unit is disclosed using double card modules with each module having an X wire system common to both cards, and further having several Y wire systems, one per bit position (bit plane). The module holds decoders for X and Y wire systems, driven by a predecoder system common to all modules and external thereto. The Y wire systems operate with anticoincidence, the sense wire system is a double wire system, each wire being rectangularly looped as threaded through half of the cores of th...