An active memory for use in data processing apparatus for storing information data relating to a system defined by several parameters, each capable of taking a finite number of values, called situations. Each of these situations may be changed in value by a finite number of variations, called actions. For each parameter, a recording center is provided consisting of a matrix having two dimensions, one of which is allocated to the situations (i.e., the values of the parameters) and the other to th...

There is disclosed an apparatus which houses a delicate memory element which is the size of a human hair. The apparatus is characterized by high packing density on the order of 25-50 elements to the inch. Parallel, enclosed channels are formed in an insulating material and are dimensioned so that the magnetizable wires are held in position therein without being stressed during variations in temperature as well as for facile insertion and removal both during manufacturing and repair operations.

An electronic memory cell consists of a bistable circuit and three access paths. Two of the access paths are used to control the state of the bistable, one of these paths being used to set the bistable, to one of its two stable states and the other of these access paths to set the bistable to the other stable state. A low impedance path is provided between one of these two access paths and the third access path in dependence on the state of the bistable to permit read-out of the memory cell.

A memory analyzer is provided with a disturb mode for selectively writing complemented test data into a computer memory. The writing operation is repeated a number of times, for example, 5,000 write cycles, and the data is thereafter read out and compared to the original data to detect errors. Hence, the effect of repeated write operations in selected locations on data in non-selected locations can be determined. One feature resides in the provision of a "B increments A" mode whereby access to a...

An array of holograms, each representing many light sources, is employed during the write operation. When one of these holograms is illuminated by a laser beam, the reconstructed light sources of that hologram illuminate a corresponding number of memory locations of a "page" of data. The light from the page then is focused onto a small area of a recording medium. A reference beam from the same laser concurrently is directed at this same small area to cause to be "written" there a hologram of the...

A memory system having a plurality of control lines, to individual lines of which impulses from a source of constant current may be selectively applied, each line being provided with inductive feed, and having a termination at the feed end thereof at least corresponding approximately with its wave resistance, the other ends of the parallel control lines being interconnected at least in groups with return flow being effected over other of associated lines whereby such connecting points are not le...

A memory unit comprising an electronic valve component having a very high-input impedance and including a control electrode and two output load electrodes. An input signal storage means is connected to the control electrode. An output means is connected between one of the output or load electrodes and a voltage supply. A zero adjustment impedance means is connected between that one of the output electrodes and the voltage supply to adjust current flow through the output means when no input signa...

A ferrite-core memory system employing a specimen magnetic core or memory device, having the same operating characteristics as the memory elements, to generate the requisite strobe pulses for addressing the memory.

This specification discloses a memory circuit characterized by a field effect transistor having its gate connected with a capacitor means, a memory setting means for charging the capacitor means, and a memory resetting means for discharging the capacitor means. The memory setting means and the memory resetting means incorporate inverting circuits to enable using an economical junction field effect transistor in the memory circuit and yet have the memory circuit remain compatible with conventiona...

A memory circuit, which is preferably of integrated circuit construction, includes three insulated gate field effect transistors. Data is stored by the capacitance between the drain and source of the first transistor. Information inputs are supplied to an input terminal and then through the drain and source electrodes of the second and third transistors to the gate electrode of the first transistor. The second and third transistors are conductive only when a gate signal, which preferably is a pu...