A magnetic bubble memory is placed in a canted, static magnetic field to produce a holding bias for the magnetic bubbles in addition to the bubble generating bias. When a rotating magnetic field is applied to move the bubbles, a static bias is also applied to cancel out the holding bias.

A memory device is provided for an integrated injection logic (I.sup.2 L) device in solid state form by a resistor connected at one end to the logic device, and a diode having its cathode connected to the other end of the resistor at a programming junction, and its anode connected to a common point. If the diode conductors are melted or deformed by reverse diode current from the programming junction to the common point, a low impedance path is formed, and the logic portion is provided with a fir...

An memory device having a stable write function and operable with low power consumption is disclosed. The memory device comprises a plurality of digit live pairs, a plurality of memory cells, a bus line, selection means for operatively and selectively transferring a logic level of one digit line of one digit line pair to the bus line and a plurality of digit drive circuits, each of the digit drive circuits being responsive to a first logic level of one digit line of the associated digit line pai...

A memory unit having a multiplicity of storage locations for the temporary storage of series of groups of data signals. When the data groups are being stored in a memory location, index signals are developed that not only identify the location of the stored signal group, but when applied to the memory unit cause the data group to be withdrawn from the memory unit. The memory unit is comprised of a first addressable multiplicity of storage locations; a second addressable multiplicity of storage l...

A nonvolatile memory, especially an electrically erasable and programmable read only memory (EE-PROM) includes an array of memory cells. In each of the memory cells four transistors are formed, that is a read transistor and a first selecting transistor connected in series, and a write-erase transistor and a second selecting transistor connected in series. The write-erase transistor has a floating gate partially provided with a thin insulation layer thereunder. The read transistor also has a floa...

A memory device which is stable in operation and operable at high speed is disclosed. The memory device comprises a plurality of pairs of digit lines, a plurality of sense amplifiers having a pair of input terminals, a plurality of pairs of gating means and a plurality of memory cells and is characterized in that the pair of input terminals of the sense amplifiers are operatively coupled through the pair of gating means to the pair of digit lines.

A memory device having a large memory capacity which can be utilized either as a random access memory or a serial access memory is disclosed. The memory device comprises memory cells arrayed in a matrix form and a shift register whose output is used for selecting the memory cells.

A semiconductor memory is provided with a hook structure composed of first to fourth regions and is capable of non-destructive readout. The third and fourth regions of the hook structure are both made floating and each form one of main electrode regions of each of a write and/or refresh transistor and a readout transistor. Carriers which are injected from the other main electrode region of the write transistor are stored as excess majority carriers in the third region and majority carriers of th...

In a semiconductor memory which is provided with a memory cell array, word lines and bit lines for selecting a desired one of memory cells of the memory cell array and a detector circuit for detecting a read current of the selected memory cell, the detector circuit is composed of a pair of transistors having their bases cross-connected so that a hysteresis characteristic is provided by flowing a current in the transistors, and the current is controlled by a hysteresis control circuit to flow onl...

A memory buffer is provided between a receiving system and a digital computer to provide an indication of the number of times pulses from the same source have been received in a predetermined interval of time upon interrogation of the memory buffer by the digital computer while such memory buffer continues to function without interruption during the interrogation process so that information from pulses received during such interrogation by the digital computer is retained.