A processor core adopts a pipeline processing method and has an interlock mechanism. A built-in accelerator executes a specific processing in place of the processor core. When a processing is executed by the built-in accelerator and there is no processing to be executed by the processor core, the interlock mechanism stops and restarts the pipeline processing in response to a start of processing and a processing completion of the built-in accelerator, respectively. A processing-completion waiting...

A microprocessor is provided whose power consumption is reduced optimally according to an execution instruction code and an operational mode. In addition to a first PLA used in a normal operation, a second PLA dedicated for execution of certain instructions frequently used in a slow mode is provided. When instruction codes and state signals to be executed in the slow mode match data set in the second PLA, the operation of the first PLA is stopped, and the microprocessor is controlled according t...

A translation lookaside buffer has a plurality of entries in which address translation information obtained by translating a virtual address into a physical address is registered. The entries each have a priority bit that is set when the registered address translation information is required to be resident. At the time an entry substitution request occurs while the priority bits of all the entries are in a set state, a control circuit for controlling the translation lookaside buffer chooses as a...

The present invention provides a microprocessor which enables task switching with a small time overhead. Upon reception of input of an interrupt control signal during execution of a task-1, a first program counter is switched to a second program counter and a first register file is switched to a second register file to start execution of a task-2. During the execution of the task-2, a task switch controller controls switches to select the first program counter, first memory devices of a processi...

For the tradeoffs between a lower consumption power of a microprocessor and its process speed, a plurality of clocks and power supply voltages are supplied to each of functional units 104 to 107 and a clock switching circuit and a power switching circuit are provided in each of the functional units. When a program mainly using a particular functional unit, e.g., FPU 106, is executed, the operation speed of FPU 106 is raised more than that in a normal operation mode. To this end, a consumption po...

A wait signal formed by a program wait circuit incorporated in a microprocessor is transmitted to outside circuitry, such as a slave microprocessor or a direct memory access control device. Thereby an outside device assumes the functions of bus master which is incorporated into a wait operation for access to a memory unit. With such a construction, a microcomputer system comprising a plurality of devices to be made into a bus mask can be simplified.

The invention relates to a microprocessor having a plurality of components which are selected from registers (14,16), arithmetic logic units (30,32), memory (36,38), input/output circuits and other similar components where the plurality of components are interconnected in a manner which allows connection between some of the components to be varied under program control.

A microprocessor comprises a calculation unit that (i) includes partial calculation units each operable to perform partial data calculation, and (ii) is operable to perform data calculation on N or less bits, where N is a total number of bits on which the partial calculation units are to perform data calculation. The microprocessor, when having the calculation unit perform data calculation according to an instruction fetched from a memory, controls the partial calculation units depending on a bi...

The invention relates to a microprocessor having a plurality of components which are selected from registers (14,16), arithmetic logic units (30,32), memory (36,38), input/output circuits and other similar components where the plurality of components are interconnected in a manner which allows connection between some of the components to be varied under program control.

When a decision circuit (217) incorporated in a control circuit (21) in an instruction decode unit (2) in a microprocessor (1) decides that an integer operation unit (4) can not execute a following sub instruction, the decision circuit (217) controls each of selectors (211, 214, and 215) and an exchange circuit (216) so that a memory access unit (3) that has already executed a preceding sub instruction can execute the following sub instruction.