A microprocessor employs pipelined architecture and comprises a first execution processor for executing and processing a first kind of instructions among decoded instructions according to microprogram control, a second execution processor for executing and processing a second kind of instructions which are different from the first kind of instructions according to hardwired control, and a controller. The controller issues decoded instructions in a program sequence, selectively determines for eac...

A microprocessor, comprising a first set of functional units capable of performing parallel data operations, a second set of functional units capable of performing parallel data operations, and a data interconnection path connecting the first and second functional units.

On a microprocessor chip mounting a central processing unit (CPU) for controlling the entire operation of electronic equipment and a digital signal processor (DSP) for processing a specific signal in the electronic equipment, an instruction cache for temporarily storing a DSP program and a cache controller are additionally mounted, and the DSP program and a CPU program are stored in an externally provided instruction memory. The cache controller controls the DSP to wait and interrupts the CPU wh...

In a microprocessor including a data memory device a simple checking circuit is provided for reading out the data onto a data bus line to check whether the data must be debugged. The checking circuit reads out data stored in an accumulator, register, etc. onto the data bus line. The checking circuit allows the microprocessor to operate normally in the absence of a checking signal and respectively connects the accumulator, register, or RAM outputs to the data bus in accordance with the timing sig...

A microprocessor includes an internal data memory, made up of a plurality of memory cells, each of which includes first and second inverter circuits. In selected memory cells, the logic state of the cell is predetermined upon initiation of the power supply by arranging the inverters of each cell such that they have different transistor ratios. The difference in ratio may be effected by altering the channel width or length of one of the constituent transistors of the respective inverter circuit.

A microprocessor has N processing units, a detector for detecting a branch instruction (k-th instruction) which comes first in the instruction sequence of N instructions, function logic for effecting control such that the first to the k-th instructions are executed with the (N-k+1)-th through the N-th processing units. However, when parallel processing is possible, the function logic operates such that the first through the N-th instructions are executed in sequential order by the first through ...

A microprocessor system having at least two separate scale integration devices. A first of the two large scale integration devices is a central processing unit formed on a single semiconductor die, and the second large scale integration device is a memory circuit formed on a separate single semiconductor die. The term "die" as used herein is conventional and refers to a unitary semiconductor body or chip. The central processing unit requires an external program counter which contains memory addr...

A single chip large scale integration processor possesses its own on-chip control storage array while including the ability to also address supplemental off-chip control storage and to use such off-chip supplemental storage in substitution for portions of the on-chip storage. The processor further includes simplified arithmetic and logic (ALU) circuitry wherein the adder circuit has portions selectively gated to perform other functions with a reduced logic circuit requirement. Processor function...

Two-unit architecture for a microprocessor having one unit to execute program instructions and another unit to fetch the instructions in their proper sequence, being arranged to permit the overlap of fetch and execute cycles to increase program execution speed. Each unit includes a register array for storing operands or addresses, each array having two independent read ports and two independent write ports. In the execution unit, the register array stores operands, read from a memory by the fetc...

A microprocessor with a bus structure for carrying address and data signals wherein an address may be modified by an index value for indirect addressing by deriving said index value from an index register or a control word field. Immediate addressing is provided on branch instructions by providing two separate incrementing paths to avoid loss of a machine cycle during branch.