An arrangement with a microprocessor, particularly a microprocessor for use in a chip card is described. The arrangement includes a microprocessor which is connected to at least a USB interfaces and an ISO interface for exchanging data signals. A selection unit within the microprocessor may be configured to select between the USB and ISO interfaces, and a switching unit within the microprocessor may be configured to subsequently switch between the USB and ISO interfaces by initiating an internal...

The microprocessor device has a central processing unit in which the instructions that are stored in a program memory are converted into arithmetic or logical combinations for controlling the different components of the microprocessor. A data and/or control line bus enables data transfer and access to CPU-internal and/or peripheral-bound special function registers, which are assigned to the central processing unit. A coherent memory block with memory cells of the random access type is assigned t...

A debugging processor includes a bus control unit for transmitting and receiving data to and from an external, an instruction execution unit receiving an instruction code from the bus control unit for executing the given instruction, and an interrupt control unit for notifying the instruction execution unit of an interrupt request. The debugging processor also comprises a debug interrupt response control unit having a priority higher than that of the interrupt control unit and having a fixed bra...

A microprocessor system is configured by connecting an n/2-bit memory and/or I/O to an n-bit microprocessor. The system has a read/write controller for enabling/disabling a read/write control signal for accessing the memory and/or I/O, an address latch counter for latching and updating the address, a bus converter for converting the data bus through which the data is transferred, and a timing generator. The timing generator comprises a detector for detecting that the instruction executed by the ...

A camera having a microprocessor made receptive of various photographic informations through interrupt processing. The information at a higher priority level of said various photographic informations such as a release signal, a photometry start signal and a photometry introduction signal is fed to said microprocessor by the interrupting operation having a shorter period than that of the information at a lower priority level. The interrupt processing are periodic ones, and wherein an inequality o...

A special reset function is provided in the CPU, using the same control input to the CPU as the normal reset, to reset only the program counter to facilitate the use of a single CPU in a microprocessor development system.

When a coprocessor communicates a plurality of data items with a master processor and a memory according to a bus access cycle activated by the master processor, the coprocessor is supplied therein with information indicating a data storage position as a data transfer source or destination. The master processor and coprocessor independently monitor the number of the sequence of data transfers or the end of the sequence of data transfer operations. As a consequence, when executing a sequence of p...

An apparatus and method is disclosed for the protection of computer programs through the use of the principles of conditional inversion and permutation. These security features are designed as part of the chip in a fashion to minimize the changes required to any existing microprocessor design and to be transparent to firmware execution. The programs are first encrypted by permutation which reorders the lines according to an allocated scheme and then conditionally inverted through a set of dual i...

A microcomputer that is easy to use and connected direct to such memories as dynamic and static RAM's and to other peripheral circuits. The microcomputer has strobe signal output terminals CASH*, CASL* and RAS* for direct connection to a dynamic RAM, and chip select signal output terminals CS0* through CS6* for outputting a chip select signal in parallel with the output from the strobe signal output terminals. The microcomputer further includes address output terminals for outputting a non-multi...

A versatile readily serviced transaction terminal includes a credit card control mechanism, a user keyboard, a user display, a document handling system for cash and printed transaction statements, and a system for controlling terminal operation. The terminal receives a user credit card having a magnetic stripe with prerecorded account information, reads the account information, and then receives a user personal ID number through the keyboard. As an available option, the terminal may require a pr...