A microcomputer that is easy to use and connected direct to such memories as dynamic and static RAM's and to other peripheral circuits. The microcomputer has strobe signal output terminals CASH*, CASL* and RAS* for direct connection to a dynamic RAM, and chip select signal output terminals CS0* through CS6* for outputting a chip select signal in parallel with the output from the strobe signal output terminals. The microcomputer further includes address output terminals for outputting a non-multi...

Microprocessor architecture for an address translation unit which provides two levels of cache memory management is described. Segmentation registers and an associated segmentation table in main memory provide a first level of memory management which includes attribute bits used for protection, priority, etc. A second page cache memory and an associated page directory and page table in main memory provide a second level of management with independent protection on a page level. eyboard

Interface circuitry (24) is provided which automatically detects which of two types of microprocessor is connected to the interface and configures the interface accordingly. A "type" flip-flop (36, 38) is initially set to expect a first type of microprocessor (10) and the interface is configured to expect a read and a write strobe. When a write cycle is performed by a second type (14) of microprocessor, the "type" flip-flop changes state and reconfigures the interface to expect a data strobe and...

A method for processing address translation exceptions occurring in a virtual memory system employing demand paging and having a plurality of registers and a real storage area, includes the steps of: (a) temporarily storing for each storage operation; (i) the effective storage address for the operation; (ii) exception control word information relative to the ones of the registers involved in the operation and the length and type of the operation; and (iii) any data to be stored during the operat...

A microprocessor control system for use in an asynchronous data communication system and comprising a receive microprocessor and a transmit microprocessor along with a paged memory for storing channel line tables. Separate receive and transmit channel number registers control access to the paged memory. Control means is provided preferably in the form of a programmable memory for controlling the sequenching of channel numbers whereby one microprocessor is adapted to access channels in an increme...

A microprocessor capable of supplying a stable internal clock signal even at the time of mode switching. A clock supply control circuit is connected between a clock generator circuit (PLL) and synchronous circuits (integer unit, instruction cache, data cache). The clock supply control circuit includes a bus interface unit, OR gates, and first and second delay circuits. With this microprocessor, when operations of the synchronous circuits are to be started, the supply of the internal clock signal...

A method for monitoring a microprocessor and a circuit arrangement having a microprocessor are described. A microprocessor is monitored using an assigned watchdog. The watchdog monitors whether reset pulses are received within a time interval of predetermined duration. If the reset pulse is received, the time interval is reset and restarted. If reset pulses are not received, a reset of the microprocessor is initiated. In suitable operating phases of the microprocessor, a check function of the wa...

In a microprocessor configuration, data is temporarily stored in a cache memory or a register bank. A respectively assigned cryptographic unit ensures that the data is encrypted or decrypted when the cache memory or the register bank is accessed. The keyword which is used here is changed if the cache memory or the register no longer contains any valid data to be read out. As a result, an increased protection is obtained against unauthorized monitoring of data and program sequences.

There is provided a programmable controller comprising a standard microprocessor having output address terminals and input/output bi-directional data terminals and means for providing a binary code on the data terminals indicative of the status of the machine cycle to be processed by the microprocessor. This programmable controller includes a logic decoder means for producing a selected signal in response to logic signals on selected address terminals and in the status binary code of the data te...

An FM tuner control circuit contains a digital frequency synthesizing control circuit, digital computer means including a microprocessor, a memory circuit, and a manual control circuit for digitally tuning the tuner to any desired FM station. The memory circuit includes a read-only memory containing programs for the microprocessor and a random-access memory in which a group of predetermined station frequencies can be stored. The control circuit also includes a call letter display circuit, a freq...