The disclosed microprocessor support system provides a total "laboratory" environment for developing and testing application software as well as for debugging the microprocessor-based application machine itself. The microprocessor support system contains a time shared minicomputer equipped with a full set of peripherals which functions as the main or operating system. A data link connects this operating system with test equipment located at the site of the application machine. This test equipmen...

A method and apparatus for bit manipulation in a digital processor being suitable for executing a plurality of instructions stored in a memory and carried from said memory in accordance with a plurality of machine cycles, each of said instructions including an operational code. A decoder generates a bit mask in response to an operational code. The bit mask generated is in binary digits which are the complement of 2.sup.i where i is the number in base 10 represented by the three least significant...

There is provided a programmable controller comprising a standard microprocessor having output address terminals and input/output bi-directional data terminals and means for providing a binary code on the data terminals indicative of the status of the machine cycle to be processed by the microprocessor. This programmable controller includes a logic decoder means for producing a selected signal in response to logic signals on selected address terminals and in the status binary code of the data te...

An automatic test apparatus coupled to a bit-directional internal data and control bus of a programmed microprocessor-based system tests the performance of the system in real time. Signal responses of the bus within a known good system are compared in real time to signal responses on the bus of an unknown system in order to identify faults. Faults are isolated by a sequential algorithm which stops operation at the occurrence of the first fault and thereupon traces the error to the subsystem or c...

There is provided a programmable controller comprising a standard microprocessor having output address terminals and input/output bi-directional data terminals and means for providing a binary code on the data terminals indicative of the status of the machine cycle to be processed by the microprocessor. This programmable controller includes a logic decoder means for producing a selected signal in response to logic signals on selected address terminals and in the status binary code of the data te...

Methods and apparatus, including computer program products, implementing and using techniques for reducing the power consumption of a microprocessor. One or more signal transitions in an instruction set of a microprocessor are profiled. A probability of occurrence is assigned to each instruction in the instruction set. A binary operation code is assigned to each instruction, based on the probability of occurrence for the instruction. The instructions having the highest probability of occurrence ...

A microprocessor EMI shield is configured for isolating EMI emissions from the microprocessor, and grounding any electric potential caused by EMI emissions detected by the microprocessor heat sink. The microprocessor EMI shield includes a low-impedance conductive surface sufficient for conducting electric potential induced based on EMI emissions from the microprocessor. The microprocessor EMI shield also includes an array of apertures for accommodating the respective microprocessor pins. The arr...

The present invention provides a microprocessor capable of improving the throughput of a CPU. Module like the program ROMs in which instruction accesses are concentrated by a CPU are put together in a first Princeton bus, and modules like the external bus I/F, SDRAM I/F, peripheral bus I/F in which data accesses are mainly concentrated are put together in a second Princeton bus. Therefore, the instruction access and the data access can be carried out in parallel with respect to the buses of the ...

A cache controller is connected to a processor and a main memory. The cache controller is also connected to a cache memory that can read and write at a speed higher than the main memory. The cache memory is provided with a plurality of cache lines that include a tag area storing an address on the main memory, a capacity area storing a capacity value of a cache block, and a cache block. When a read request is executed from the processor to the main memory, the cache controller checks whether the ...

A microprocessor used in a pair with a baseband processor for performing the baseband processing, is provided with a central processing unit for calculation processing, a counter capable of measuring time in the calculation processing by the central processing unit, and an interface which enables the baseband processor to read the counter. By making the baseband processor read the counter, the processing by the baseband processor is synchronized with the processing by the central processing unit...