A method of emulation or functional testing of a first microprocessor in its functional environment including one or several peripherals and at least one internal bus of communication between this first microprocessor and its peripherals, from a second microprocessor, consisting of deactivating the first microprocessor, using the communication bus(es) to communicate between the two microprocessors and the peripheral(s), and activating the second microprocessor, wherein the first microprocessor c...

An apparatus, system, and method for measuring parameters, measuring or determining capacitance, producing a digital output that is dependent upon a capacitance, or converting a variable capacitance output, of a sensor capacitor for example, into a digital format. By activating and deactivating pins, a microprocessor may form various circuits, for instance, each containing a resistor and a different capacitor and, in some embodiments, without the use of intermediate switching components. The mic...

A power delivery system delivers a relatively constant voltage to a microprocessor with low inductance and low resistance. The system includes a motherboard, an integrated circuit (IC) mounted on one side of the motherboard, a capacitor bank mounted on the opposite side of the motherboard; and a power converter mounted on the side of the motherboard opposite the IC. The IC contains a microprocessor that receives power from the power converter and capacitor bank. A short electrical path between c...

A microprocessor that executes a repeat prefetch instruction (REP PREFETCH). The REP PREFETCH prefetches multiple cache lines, wherein the number of cache lines is specifiable in the instruction. The instruction is specified by the Pentium III PREFETCH opcode preceded by the REP string instruction prefix. The programmer specifies the count of cache lines to be prefetched in the ECX register, similarly to the repeat count of a REP string instruction. The effective address of the first cache line ...

A data processing chip with a flexible timing system and method for supplying clocks to a digital data processing system useful for power conservation. A phase locked loop generates a master clock from which a core clock and a system clock are derived. The frequency of each of the core and system clocks is independently controllable relative to the master clock and can be changed on the fly with glitch free and jitter free operation. The data processing chip is well suited for use in hand held e...

A single shared processing path is used as contexts are switched during processing. Each unique context is processed using a corresponding unique pipeline. If a pipeline that is executing under one context stalls, processing is switched in the shared processing path to another pipeline that is executing under second context. New pipelines are enabled for execution by borrowing a clock cycle from the currently executing pipeline. In some cases contexts are assigned various relative priority level...

Alarms are often required on various vehicles and equipment such as fork lifts, dump trucks, bulldozers, etc. An alarm is disclosed controlled by a microprocessor, which is an integral part of the basic circuit. The alarm has a flat diaphragm, and a novel acoustic lens. The acoustic lens is constructed such that sound emanating from the center of the diaphragm has a direct path to the outside of the alarm. Sound produced around the periphery of the diaphragm must pass through a path containing s...

A microprocessor that executes a repeat prefetch instruction (REP PREFETCH). The REP PREFETCH prefetches multiple cache lines, wherein the number of cache lines is specifiable in the instruction. The instruction is specified by the Pentium III PREFETCH opcode preceded by the REP string instruction prefix. The programmer specifies the count of cache lines to be prefetched in the ECX register, similarly to the repeat count of a REP string instruction. The effective address of the first cache line ...

Disclosed herein are an IC card and a microcomputer which have implemented the strengthening of security and the speeding up and enhancement of signal processing for the security. In an IC card, which is supplied with an operating voltage by an electrical connection between each of external terminals and a read/write device, and includes an input-output operation of data with an encoding process or a decoding process, a disturbance-aimed processing operation is included in the encoding process o...

A secure microprocessor is designed using quad-coded logic which is similar to dual-rail encoded asynchronous logic except that the `11` state propagates an alarm. The alarm signal obliterates secure data in its path. Quad-coded logic provides resilience to power glitches and single-transistor or single-wire failures. The already low data dependency of the power consumption makes power analysis attacks difficult, and they are made even more difficult by inserting random delays in data and contro...