A network amplifier is provided. The network amplifier includes a variable equalizer having at least one control input and a variable attenuator having at least one control input. The network amplifier also includes at least one amplifier circuit that is coupled in series with the variable equalizer and the variable attenuator in a signal path of the network amplifier. The network amplifier also includes an automatic gain control circuit with a processor that monitors signals in the signal path ...

method of preventing an electronic file containing a computer virus from infecting a computer system using the Symbian.TM. operating system, the method comprising the steps of scanning files using an anti-virus application, and if an infected file is identified, maintaining the file in an open non-sharing state, whereby other applications running on the computer system may not operate on an infected file.

A processor-based device includes a processor, a trace module, a plurality of data input/output pins, and an input/output interface circuit. The input/output interface circuit, when operating in a trace mode, externally outputs trace data signals from the trace module to an external device via at least one of the data input/output pins. When in a normal mode, the input/output interface circuit transfers data from the processor core to the data input/output pins and transfers data received at the...

A host control interface for use in interfacing an external host processor with internal control/status registers of an integrated circuit is provided. In accordance with the teachings of the present invention, the control interface selectively couples the integrated circuit with an interchangeable one of a variety of host processor types. In one embodiment, the control interface supports processors having a multiplexed address/data port as well as processors having separate address and data por...

A microprocessor including memory storage into which ISA customer code routines can be stored after having been decoded into their machine-native microinstructions. The customer code store is not subject to eviction and the like, as a cache memory would be. ISA level code can specify a routine for storage into the customer code store, at a time prior to its execution. The customer code store thus serves as a write-once execute-many library of pre-decoded routines which ISA level applications can...

A microprocessor used in a pair with a baseband processor for performing the baseband processing, is provided with a central processing unit for calculation processing, a counter capable of measuring time in the calculation processing by the central processing unit, and an interface which enables the baseband processor to read the counter. By making the baseband processor read the counter, the processing by the baseband processor is synchronized with the processing by the central processing unit...

A microcontroller for security applications includes an encryption unit between a bus and a functional unit. The encryption unit includes a gate and a key register. A memory is provided with a further encryption unit whose gate is connected between the register and the gate of the first encryption unit. As a result, the transferred information item is available in encrypted form at any point on the bus.

A microprocessor uses broadcast state renaming to reduce processing delays and microcode overhead which would otherwise result from rebroadcasts of state due to register renaming. The microprocessor comprises a memory execution unit, a microcode sequencer, and various functional units. The memory execution unit includes a segment register, content of which represents state of the processor. The microcode sequencer sets an identifier field in at least some microinstructions, indicating which of m...

A method for verifying an integrated circuit design includes generating verification coverage information by simulating the operation of the integrated circuit. The verification coverage information is then analyzed to determine a set of missing coverage states. A set of verification directives based on the set of missing coverage states is composed and a set of test cases is generated, based on the verification directives, to simulate the missing coverage states. Analyzing the verification cove...

The present invention provides a digital-based mechanism for adjusting the power consumption in an integrated digital circuit such as a processor. The processor includes one or more functional units and a digital throttle that monitors activity states of the processor's functional units to estimate the processor's power consumption. One embodiment of the digital throttle includes one or more gate units, a monitor circuit, and a throttle circuit. Each gate unit controls the delivery of power deli...