A procedure and processor are disclosed for avoiding lengthy delays in debug procedures during access by a memory mapped peripheral device. The processor includes in-circuit emulation means comprising one or more scan chains or serially connected registers for access by an external host computer system. The procedure comprises: a) the host computer system carrying out a debug procedure via said scan chains, and selectively interrupting such debug procedure for access to a peripheral memory mappe...

A method is provided for reducing the power consumption of a pipelined microprocessor system arranged to run a program stored in a memory. The method comprises duplicating at least one branch instruction so as to reduce the number of transitions on the bus between the microprocessor and the memory when the program is executed.

A computer architecture and programming model for high speed processing over broadband networks are provided. The architecture employs a consistent modular structure, a common computing module and uniform software cells. The common computing module includes a control processor, a plurality of processing units, a plurality of local memories from which the processing units process programs, a direct memory access controller and a shared main memory. A synchronized system and method for the coordin...

A wireless communication device is described having a transmitter that generates electromagnetic interference when operating in a transmit mode. The wireleess communication device comprises a clock circuit including a first clock element configured to generate a first clock output, and a second clock element configured to generat a second clock output. Also included is a controller configured to switch between the first clock output and the second clock output when the transmitter is operating i...

A microprocessor retention system and method is disclosed in which a base of a retention system is coupled to a method board. The base of the retention system includes a number of slots or openings for receiving a microprocessor and an associated heat sinks. The cover of the retention system includes a number of individually coiled springs. When the cover is secured to the base, the springs apply a compressive force to the heat sinks, placing the heat sinks in thermal contact with the associated...

A CPU executes program instructions which result in valid and invalid intermediate results. By selecting the desired intermediate results, a program is able to be successfully executed. Analysis of the intermediate results must avoid plausible wrong results. A programmable feature allows the instruction decoder to provide plural answers, including plausible wrong answers. Instruction output selection logic selects a predetermined buffer, and this permits further microprocessor operation with the...

A cache control apparatus for an information processing system having a cache memory with a plurality of ways is disclosed, in which the hardware amount is reduced and the delay of the response time is minimized. At the time of cache access, each way is indexed by time division, and when updating the cache, a way to be updated is designated thereby to update the cache tag and the cache data. The data indexed by time division can be judged for a hit each time of indexing or alternatively, the dat...

A clock circuit comprises an analog clock element, a digital clock element, and a controller. The analog clock element is configured to generate an oscillating output. The digital clock element is configured to generate a digital clock output. The controller is configured to switch between the analog clock element and the digital clock element. The oscillating output and the digital clock output have substantially equivalent frequencies.

A method, processor, and data processing system for enabling maximum instruction issue despite the presence of complex instructions that require multiple rename registers is disclosed. The method includes allocating a first rename register from a first reorder buffer for storing the contents of a first register affected by the complex instruction. A second rename register from a second reorder buffer is then allocated for storing the contents of a second register affected by the complex instruct...

A microprocessor a microprocessor includes: a processor module executing an instruction to generate trace information including the information of the kind and the length of the instruction; an application processing circuit operating in cooperation with the processor module to process a specific application; an address calculating circuit calculating an execution address for executing the instruction based on the information of the instruction length; a data obtaining circuit obtaining data fro...