This multiprocessor circuit has interruption restriction circuits connected between the interruption line, which is provided for inputting interruption signals, and each of the CPUs connected in parallel. The interruption restriction circuits restrict the input of interruption signals to each CPU under certain conditions. Each interruption restriction circuit counts the number of interruption signals received by each corresponding CPU during a specified period set at the timer, using a counter. ...

The invention relates to a multiprocessor system having plural processors and an optical bus shared by the plural processors, and intends to simplify the cache control, reduce the volume of hardware, and shorten the memory access processing time. For this purpose, the multiprocessor system of the invention includes a shared memory, a cache memory connected to the shared memory, an optical bus connected to the cache memory, and plural processors connected to the optical bus, which access to the c...

As much tag information as corresponds to the number of blocks stored in main memories is stored in tag memories. The tag information indicates whether or not a processor belonging to a node other than the nodes containing tag memories has made an access request and the contents of a cache have been rewritten. Bus bridges perform cache coherency control, referring to the tag information. When the tag information indicates "Modified," the bus bridges stop the data read from the main memories and ...

An asymmetrical multiprocessor system has a main storage or macroprocessor connected under control of a microprocessor for initiation and termination of operation of the macroprocessor. The macroprocessor after being started by the microprocessor runs until a check condition in the macroprocessor occurs, a non-executable operation code (OP code) in the macroprocessor is encountered, or the microprocessor wants control. When the macroprocessor stops the microprocessor is interrupted. The interrup...

A multiprocessor system is described in which a plurality of central processor units share the same main memory over a common asynchronous bus. Each central processor directs all memory requests to its own high speed cache memory. If the request is to read data from memory, the cache memory control determines if the addressed data is present in the cache memory. If so, the data is transferred to the processor without accessing main memory over the bus. If the data is not present in the cache mem...

A multiprogrammable, multiprocessor computer system is disclosed including at least one central processor for performing arithmetic and logic operations, at least one input/output processor for performing input and output operations, storage means connected with each of the processors and adapted for storing central processor programs associated with the central processor and channel programs associated with the input/output processor, and a multiprocess controller connected to each of the proce...

A numerical control system includes a main processor which performs such functions as interpolation and outputting of motion command signals to the servomechanisms on a machine tool. A separate programmable interface processor connects to the main processor bus structure and it operates as a programmable controller to control the discrete digital I/O devices associated with the machine tool. A third processor couples through a serial data link with the main processor and it operates to service p...

A distributed multiprocessor communication system, wherein the central processing unit (CPU) is relieved of the burden of bus management by a scheme which multiplexes the interprocessor module communications bus, to which all processors are guaranteed access, so that only an addressed CPU may be interrupted from performing its dedicated data processing function. Associated with each independent processor is a communications interface unit or communications network routing unit which relieves the...

A multiprocessor system has plural autonomous digital data processors operable to communicate individually with a common storage system. Each processor has its own clock. The timing control means selectively uses any one of the individual processor clocks for timing the communication of its or any other processor with the common storage system.

Disclosed herein is a multiprocessor control for a communications switching system wherein an instruction stored in the program order register of one processor is decoded both within that processor and within another processor to initiate and control cooperative data processing operations in both processors. Data and control information is exchanged between processors by means of cross-coupled gating buses which are employed within each respective processor for communication among its own regist...