A cache coherency system and method which switches the data consistency maintenance protocol used for a given piece of shared data at each private cache, automatically depending upon the likelihood or frequency that the processor having the private cache concerned will accesses the given piece of shared data, and the likelihood or frequency that the other processors in a multiprocessor system will access the given piece of shared data. In the preferred embodiment, the present system and method s...

A data processing system is disclosed in which a high-speed processor is added to a slow-speed processor and in which both processors have access to a first memory unit with the slow processor having access priority over the fast processor. In order to allow the fast processor to operate without losing data when a conflict occurs during a write operation, a second memory is coupled to the fast processor in which is stored all the data stored in the first memory. When the fast processor attempts ...

In a multiprocessor system, a source of description is provided in a unique work area assigned to each user program or process that references data and program stored in memory. Each description includes a first field defining the structure and format of the data, a second field specifying the location of the objects, the size of the object and any limits imposed, and a third field for controlling access and governing the data usage. Also included in each description are operating system flags w...

A task status word (TSW) is created for each task indicating, the instant location of the task, its priority and a record of synchronizing signals. Task status words are accessible from an addressable memory section for delivery to a TSW register. From the TSW register, a selected TSW effects control functions to synchronize tasks in different processors or computational units as well as input-output processors. A physical memory manager locates TSWs in response to signals, then checks the locat...

An architecture for a switching node of a communication network includes a dedicated hardware Layer 1 processing portion and a Layer 2 and 3 processing portion based on multiple programmed general purpose processors. An array of such processors are used with an arbitration scheme for selecting which of the processors is to be used for any given Layer 2 or Layer 3 process. The architecture allows the node's capacity to be expanded by simply adding more processors to handle increased traffic.

A method (and system) for executing a multiprocessor program written for a target instruction set architecture on a host computing system having a plurality of processors designed to process instructions of a second instruction set architecture, includes representing each portion of the program designed to run on a processor of the target computing system as one or more program threads to be executed on the host computing system.

A system using a sorting network to intercouple multiple processors so as to distribute priority messages to all processors is characterized by semaphore means accessible to both the local processors and the global resource via the network. Transaction numbers identifying tasks are employed in the messages, and interfaces at each processor are locally controlled to establish transaction number related indications of the current status of each task being undertaken at the associated processor. A ...

A data processing system includes a set of modules for processing data applied to the modules from a common data bus. The data is presented serially, with individual words of the data being separated by strobe signals. The time interval allocated for processing by a module extends over a plurality of data words. The processing operations of the respective modules are initiated in staggered time, the operations overlapping each other in time. A daisy chain comprising individual units in each modu...

A control arrangement for a multifunction appliance such as a cooking appliance wherein the control activity is distributed among a plurality of microprocessor based control circuits. In the exemplary embodiment each control circuit is associated with a different function of the appliance. The circuits are physically separated from one another and communicate on data bus lines. Due to the high transient conditions in such an appliance, the communications are in accordance with a redundant protoc...

A multiprocessor digital computation system for performing at least one signal-processing chain which includes a number of processes. Each process is executed by means of executing circuits including memories, computing operators and input-output couplers, which are interconnected by means of a bus system. The system includes a sequencer and an address and connection generator, wherein the sequencer includes plural process modules, one for each process to be executed, and indicates at each compu...