A multiprocessor computer system wherein memory buses of separate central processing unit systems are interfaced to an intermemory communication network for transfer of data between memories of said separate central processing unit systems. The intermemory communication network includes a plurality of preferably passive intermemory communication links being tapped for connection to link adapters interfacing a number of central processing unit systems to each intermemory communication link. The n...

The disclosure provides a unique multiprocessing (MP) method for executing on plural CPUs of the MP a uniprocessor system (UPS) program not written to run on a MP system. Separate copies of the UPS are provided in the shared main storage (MS) of the MP. A hypervisor type of control program (called a partitioned multiprocessing system, PMP) uses the MP method to enable simultaneous execution of the plural copies of a UPS on different CPUs of the MP as UPS guest virtual machines. PMP can dedicate ...

An asynchronous bus multiprocessor system where a plurality of microprogrammed processors communicate with a working memory through a common bus. Microinstructions are read out from working memory. At least one of the processors, in addition to conventional bus interface registers for latching of data, address and commands to be forwarded to the working memory through the bus, is provided with an additional interface register, devoted to the latching of a microinstruction address for a microinst...

A split-BUS multiprocessor system for acquiring data and outputting the d in digital computer format has an electronic front end that receives data from one or more sensors and converts the data to digital form. An acquisition microprocessor operating in a polling mode acquires the digital data and stores it in a data memory. An output microprocessor operating in an interrupt mode extracts the data from the data memory and routes it to appropriate display and recording devices in digital compute...

A method and apparatus for synchronizing communication between a plurality of processors which communicate with one another over a system bus wherein sending processors seek to transfer information to target processors. Means are provided for each processor to store information to be transferred, for receiving a request signal from a sending processor, and for receiving an acknowledgment signal from a target processor, wherein the sending processor provides a request signal to the target process...

A plurality of multiprocessor systems is arranged in a high speed network to allow any processor in one system to communicate with any processor in another system. The network may be configured as a multi-node dual bidirectional ring having a multiprocessor system at each node. Packets of information may be passed around the ring in either of two directions and are temporarily stored in buffer memory locations dedicated to a selected destination processor in a selected direction between each suc...

A multiprocessor system including firmware, which system is comprised of at least a plurality of central processing units and a main memory to be commonly occupied by all the central processing units. The main memory is composed of an operating system area and a firmware area. The firmware area is divided into a common firmware area utilized by all the central processing units and a plurality of independent prefix areas allotted to the central processing units. Each prefix area is operative as a...

A plurality of multiprocessor systems is arranged in a high speed network to allow any processor in one system to communicate with any processor in another system. The network is configured as a multi-node dual bidirectional ring having a multiprocessor system at each node. Packets of information may be passed around the ring in either of two directions and are temporarily stored in buffer memory locations dedicated to a selected destination processor in a selected direction between each success...

The system according to the invention comprises a central microprocessor and peripheral microprocessors. A direct-access transfer memory is provided for the communication of the processors with one another. The memory is divided into as many distinct, determined zones as there are peripheral processors. The memory is connected to two addressing buses of which the latter serves equally well to address the boxes of the memory by the central microprocessor and to address the zones of the memory all...

An electronic apparatus with processing capability dedicated to the display function. This apparatus includes a keyboard for inputting data into the processor system and a display for presentation of the output data from the processor system. The electronic digital processor system includes a memory, an arithmetic and logic unit and two central processing units that operate independently and simultaneously. The keyboard input is connected to one central processing unit and the display is connect...