Apparatus for regulating access by each of a plurality of asynchronous data processors to each of a plurality of memories, each processor being associated with one of the memories and needing both read and write access to its own memory and to the processor's memories, the apparatus including local bus circuitry to selectably permit each processor to have, or to prevent each processor from having, access to its associated memory, connecting bus circuitry to selectably permit each processor to ha...

A lock array is provided with bit positions corresponding to each line entry in an associated cache directory. When a lock bit is on, it inhibits the castout, replacement, or invalidation of the associated cache line, which operations are allowed when the lock bit is off. The lock bit may be in an off state while an associated valid bit is set on, but once the lock bit is set on the valid bit cannot be set off until the lock bit is first set off. Lock array controls operate with a replacement se...

An improved method for communicating updated information among processors in a distributed data processing system. The system includes a plurality of distributed interconnected processors each having a memory. The method includes the steps of prioritizing the processors into a predetermined order, establishing one of the processors as a control processor for the broadcast of update messages, developing an update message in at least one of the processors, selecting in accordance with the control ...

A single chip multiprocessor interface device for interfacing between two processors by connection to their bus systems, the device having a random access memory selectively accessible by the processors under the control of an arbitration latch. The arbitration latch has a bistable device the state of which determines which processor has access to the memory. The outputs of the bistable device have threshold devices which have threshold levels higher than the signal outputs of the bistable devic...

The hybrid cache control provides a sharing (SH) flag with each line representation in each private CP cache directory in a multiprocessor (MP) to uniquely indicate for each line in the associated cache whether it is to be handled as a store-in-cache (SIC) line when its SH flag is in non-sharing state, and as a store-through (ST) cache line when its SH flag is in sharing state. At any time the hybrid cache can have some lines operating as ST lines, and other lines as SIC lines. A newly fetched l...

A multiprocessor that includes a virtual file system providing a file system interface to user application code. This interface allows users to access files in many types of file systems in a consistent, file system-independent manner. In a preferred embodiment, the higher interface of the file system is the Posix file system interface, though it can be any file system interface supporting the capabilities required by a user process. The Posix file system supports regular files, pipes, fifos and...

Methods, systems, and computer program products are provided for scheduling threads in a multiprocessor computer. Embodiments include selecting a thread in a ready queue to be dispatched to a processor and determining whether an interrupt mask flag is set in a thread control block associated with the thread. If the interrupt mask flag is set in the thread control block associated with the thread, embodiments typically include selecting a processor, setting a current processor priority register o...

In one embodiment, a first processor of a multiprocessor system, encounters an exception and jumps to exception handler code at an architecture-defined exception vector. The processor is directed to a data structure which provides a programmable exception vector to additional exception handler code. This additional code may be executed as if it were located at the architecture-defined exception vector. Other embodiments are described and claimed.

Systems, methods, and device are provided for symmetric multiprocessor (SMP) systems. One method embodiment includes creating a child process for each processor in the SMP. An event address register (EAR) associated with each processor is used to record information relating to cache misses. The EAR records are analyzed for each processor and a bit vector is created for each byte of cache line that is shared by multiple processors.

In a shared memory multiprocessor system, data reading accesses and data write-back completion notifications are selected in synchronism with all of the nodes to order them. In each of the nodes, a subject address of ordered data reading access is compared with a subject address of ordered data write-back completion notification to detect a data reading operation of the same address which is passed by the completion of the data writing-back operation. Both a data reading sequence and a data writ...