In a multiprocessor system, when a store request has stalled, a signal is generated and sent to all processors indicating such a stalled store situation. In response, all processors will postpone the sending of load, or read, requests to memory until the stalled store request has completed.

An interconnection network for a plurality of process nodes, each illustratively comprised of a processor-memory pair, utilizes an hexagonal mesh arrangement of size n which is wrapped in each of the x, y, and z directions. In accordance with the invention, a unique address value is assigned to each processor node in the network, beginning at a central processor node and continuing along the x direction, and via the wrapping links, until each such processor node has a unique sequential address. ...

In a multiprocessor system, a request from a processor for data transfer between an external mass storage unit and a main memory is granted and a report indicating an event is supplied from the external storage unit if there is one to report. An event decoder decodes the reported event and makes a first decision if it is a sync-related event resulting from the execution of an instruction and makes a second decision if it is a sync-unrelated event irrelevant to execution of instructions. One of t...

The present invention provides a multiprocessor ATM exchange which permits an ATM exchange to be configured with multiple processors to provide high capacity. The CLP state management section of the common signaling processor collects load state information from the CLP load monitoring section of call control processors to manage the load state thereof, and manages the normal or abnormal state of the call control processors. The signal floating function section, when receiving an initial address...

Each housekeeping command calls for a corresponding combination of write back and flag reset operations. In laundering, a write back operation is performed for owner entries in a specified address set without invalidating those entries. In flushing, a launder is followed by a flag reset invalidating the entries in the address set. Also, the command indicates which of the valid flags should be reset. In demapping, only the flags making an entry inaccessible to the cache's processor are reset. The...

An improved system for sorting a data set of 2.sup.m keys in a parallel processor environment is disclosed. The system operatively maps a shuffle-exchange network onto a Batcher sorting network in order to produce a monotonically sorted output set. Complete and efficient sorting is achieved by shuffling a control mask applied to multiple compare-exchange elements when the data set is redundantly shuffled. A further improvement is achieved by employing an unshuffle operation to the data set and/o...

In a multiprocessor system in which at least three processors are connected to a system bus by way of which data and source and destination processor identification numbers are exchanged between source and destination processors. A third processor receives the same data and the same source and destination processor ID numbers as those received by the destination processor. Each processor detects an error in data being transmitted to the bus and detects an error in data being received therefrom. ...

In a multiprocessor system (FIG. 1), file sorting and merging operations are broken down into a series of partial-file sorts and partial-file merges which are executed in parallel by a plurality of processors (21-26). In a file sorting operation, an input file processor (24) distributes segments (201) of an input file (200) from disk (34) to a plurality of sort processors (21-23) in a round-robin fashion. Each sort processor sorts records (203) of each received segment according to a key, and st...

In one embodiment, the present invention includes a method for receiving a first memory request from a first caching agent associated with a first processor, in a home agent associated with a memory, directing the first memory request to a writeback queue of the home agent if the first memory request is a writeback request and otherwise directing the first memory request to a second queue of the home agent. In this way, circular dependencies may be avoided. Other embodiments are described and cl...

A computer having any number of processors of equal capability in the system, each processor being able to scan all peripheral devices over a common bus, with priority resolution being provided by connecting the processors in a closed loop on which is circulated a priority bit. Only the processor receiving the bit can utilize the common bus and circulation of the bit is interrupted by the processor utilizing the common bus.