Storage serialization apparatus in a multiprocessor computer system enables multiple processors to concurrently execute instructions which access storage without materially affecting performance by keeping the amount of storage locked to a minimum, i.e., a page. The duration of serialization need be only for one instruction execution time and only instruction operands need be accommodated for serialization. Each storage request is intercepted by an associative register stack where there are two ...

A binary tree multiprocessing array of plural signal processing elements, and having input/output for the array entirely through a root one of the processing elements, includes in each processing element thereof a hardware, pipelined, floating point, multiply/accumulate processing function for cooperating with a procesing element memory and a processing element input/output processing function to perform signal pattern matching of input digital signal sequences provided to and/or through the roo...

In a multiprocessor system, a program's execution that is controlled by controlling an extended process that spans a plurality of processors. The extended process comprises an user process on one processor for executing object code of the program and stub processes each on an individual one of said remaining processors for accessing system resources required for execution of the program. Each stub process gives the extended process access to the resources associated with the processor executing ...

A bus protocol system for interprocessor communications in valves polling the processors of a multiprocessor unit in an open loop fashion to determine which processors are ready to send. Upon completion of a simultaneous poll of all processors the system identifies which processor are ready to send by utilizing a send mask generated by the ready processors. The ready processors are sequentially selected as send processors and granted access to the bus for a complete data transfer cycle unless th...

A system for distributed control of a plurality of processors (UC1-UCa, UCP1-UCPb, MQ1-MQc) forming a set of processors (e.g., in a telephone exchange). Each processor is provided with a respective link coupler coupling it to a semaphore type serial link for point-to-point communication between processors. The control system comprises a network and a network distributor (DR1, DR2). The network comprises at least one clock link (H) for synchronizing data transfers, together with the following ind...

An interrupt control method for a multiprocessor system including a plurality of microprocessors wherein sections of a main memory, which is shared among the processors of the system, are allocated to store entry address data pointing to a plurality of interrupt-servicing programs for each of the several processors of the system. Interrupt commands are coded to designate different interrupt levels which are compared against mask flag bits and a master mask flag bit unique to each processor to de...

The disclosure relates to multiprocessor handling of plural queues of pending I/O interrupt requests (I/O IRs) in a main storage (MS) shared by plural central processors (CPs). An input/output processor (IOP) inserts I/O IR entries onto the queues in accordance with the type of interrupt. The entries in the queues are only removed by the CPs, after their selection by a system controller (SC) for execution of an interruption handling program. An I/O interrupt pending register in I/O interrupt con...

A number of partitions of a cellular multiprocessor (CMP) are connected to respective databases and form respective nodes of a data warehouse. Heterogeneous data stored across the nodes is accessed automatically in parallel at high speed from a user site using a simple script request containing a data source object name wherein the heterogeneous data is treated as a single data source object, the script further containing at least one method to be performed on the data source object. Respective ...

A symmetric multiprocessor system includes a first processor and a second processor for executing a multi-threaded process on packets, a first inbound interface and a first outbound interface associated with the first processor, a first task queue accessible for reading by the first processor, a second inbound interface and a second outbound interface associated with the second processor, and a second task queue accessible for reading by at least the first processor. The first inbound interface ...

A multiprocessor system is comprised of a bus and a plurality of processor modules. Each processor module includes a bus arbitration block, a bus access control block, an address output block, a data input/output block, a clock signal generating block, a stop request block for requesting the stop of supplying a clock signal, an operation processing block for processing data, and a stop control block. The stop control block stores the contents of the bus access (a type of the bus, the address and...