A memory interface and conflict resolution network for a multiprocessor system. The memory is multisectional and each section of memory has a plurality of individually addressable memory banks organized in an interleaved fashion and a section level conflict resolution network. Each processor in the system includes several ports and a gating network such that each port may access any section of memory, but access is restricted to no more than one reference per processor per clock period to each s...

A multiprocessor interrupt rerouting mechanism and method is disclosed for rerouting messages intended for a first processor to a second processor. In a fault tolerant computer system having several processors or LANs under the control of a single controller, when the controller completes a communication task requested by one of the processors, it will send an interrupt request to the requesting processor which then notifies the application process for which the communication task was performed,...

In a multiprocessor system interconnected by a bus structure that provides communication and information transfers between the processor modules of the system, each processor broadcasts a central message to all the other processors of the system on a periodic basis. A processor module not receiving the control message from a sending processor module will assume the sending processor module has failed, and operate to take over the task of the failed processor module.

A cache coherence system for a multiprocessor system including a plurality of data processors coupled to a common main memory. Each of the data processors includes an associated cache memory having storage locations therein corresponding to storage locations in the main memory. The cache coherence system for a data processor includes a cache invalidate table (CIT) memory having internal storage locations corresponding to locations in the cache memory of the data processor. The cache coherence sy...

When a fault is detected in a processor, program execution in this processor is interrupted and taken up again by a standby processor from an earlier uncorrupted state, a recovery point. Such recovery points are specially provided in the program. A save copy of the state at the recovery points is created in each case in a state save unit by recording changes compared with the respective previous state. The data memory existing in the state save unit has pairs of memory words, in which arrangemen...

In a multiprocessor system (FIG. 1), memory (22) of each adjunct processor (11-12) comprises global memory (42) and local memory (41). All global memory is managed by a process manager (30) of host processor (10). Each processor's local memory is managed by its operating system kernel (31). Local memory comprises uncommitted memory (45) not allocated to any process and committed memory (46) allocated to processes. The process manager assigns processes to processors and satisfies their initial me...

A multiprocessor configuration includes a plurality of processing groups connected to form both a first and second communication path, and an interpath connection connecting the first and second communication paths. The first and second communication paths and the interpath connection provide allow communication between processors in different processing groups even if one processing group fails and, thus, creates a discontinuity in both the first and second communication paths. One or more proc...

The present invention provides for controlling the power consumption of an element. A first power control command is issued by software for the element. It is determined if the power control command corresponds to an allowable power control state for that element as defined by the hardware. If the power control command is not an allowable power control state for that element, the hardware sets the power control at a higher level than the power control state issued by the software. A hierarchy of...

An embodiment of the invention is a technique to affinitize a thread in a multiprocessor system having N clusters of processors. A count threshold is obtained for thread affinity of the thread. A first thread count is determined. The thread is affinitized to a first cluster in the N clusters of processors according to the first thread count and the count threshold.

A design verification system utilizing programmable logic devices having varying numbers of logic processors, macro processors, memory processors and general purpose processors programmed therein is disclosed. These various processors can execute Boolean functions, macro operations, memory operations, and other computer instructions. This avoids either the need to implement logic or the need to compile the design into many gate-level Boolean logic operations for logic processors. Improved effici...