A new method and framework for scheduling receive-side processing of data streams received from a remote requesting client by a multiprocessor system computer is disclosed. The method receives data packets from the remote requesting client via a network and, for each data packet, applies a mapping algorithm to portions of the received data packet yielding a mapping value. The method further applies the map value to a processor selection policy to identify a processor in the multiprocessor system...

Multiprocessor system, having a translation lookaside buffer (TLB) in each processor, and having a structure for avoiding TLB purge overhead. Each processor node is provided with a partial main memory and a physical page map table (PPT). The PPT stores mapping between physical page number of main memory and virtual page number. Every memory access transaction for other node specifies physical address and virtual page number. Instead of strictly maintaining TLB coherency by broadcasting TLB purge...

In one embodiment, a node comprises a plurality of processor cores and a node controller configured to receive a first read operation addressing a first register. The node controller is configured to return a first value in response to the first read operation, dependent on which processor core transmitted the first read operation. In another embodiment, the node comprises the processor cores and the node controller. The node controller comprises a queue shared by the processor cores. The proces...

A multiprocessor system (10) includes a plurality of processing engines (14, 16, 18, 20, 22, 32, 33 and 35) including a software processing engine and a hardware processing engine implemented on a single silicon device defined by a single programming language and the single programming language tagged with at least one macro. The multiprocessor system further includes connectivity (37 and 40) between the plurality of processing engines defined by the single programming language and by the single...

Access control to protected resources in a multiprocessor system is implemented without additional use of the processor bus. A bridge interconnects each processor with shared resources. The bridge has a semaphore corresponding to each protected resource indicating if the corresponding resource is available. The bridge halts a processor requesting access to any resource having a corresponding semaphore indicating the requested resource is not available.

A single coder/decoder shared among several multiprocessors in a digital signal processing system through time-division multiplexing between multiple processors to enhance signal processing capabilities by assigning different digital-to-analog channels to different processors for digital-to-analog conversion, while allowing all processors to operate on the same analog-to-digital data for analog-to-digital conversion, thereby resulting in chip area reduction and power consumption saving.

A method of synchronizing a general network of processors, which network may contain loops, the method comprising: (a) providing clock signals at each of the processors, said clock signals having a common frequency; (b) measuring the phase between clock signals of different processors at the processors; and (c) adjusting the phase of the clock signals to produce local clock signals at each processor by varying the phases of the clock signals of individual ones of the processors, responsive to th...

For use in a multiprocessor system in which a plurality of processors share a main memory via a processor bus, an error processing unit (EU) that determines an error level is provided in each processor. When an L2 cache control unit (SU) that controls an L2 cache in the write-back mode, a bus interface unit (PU), and so on, are normal and snoop processing may be continued, the snoop processing is continued in the processor, in which an error occurred, regardless of whether or not the processor i...

A memory subsystem for use with a multiprocessor computer system. The memory subsystem includes an operation block adapted for queuing an operation that misses in an L1 cache of a multiprocessor. The multiprocessor is comprised of a set of processors, preferably fabricated on a single semiconductor substrate and packaged in a single device package. The memory subsystem further includes an arbiter that is configured to receive external snoop operations from a bus interface unit and a queued opera...

A compression/decompression (codec) engine is provided for use in conjunction with a fabric agent chip in a multiprocessor computer system. The fabric agent chip serves as an interface between a first memory controller on a first cell board in the computer system and other memory controllers on other cell boards in the computer system. Cell boards in the computer system are interconnected by a system fabric. Memory data read by the first memory controller is compressed by the codec engine prior ...