A method for identifying, managing, and signaling uncorrectable errors among a plurality of clusters of symmetric multiprocessors (SMPs) detects, manages and reports data errors. The method allows merging of newly detected errors, including memory, cache, control, address, and interface errors, into existing error status. Also, error status is distributed in several possible formats, including separate status signals, special UE (uncorrectable errors) ECC codewords, encoded data patterns, parity...

A system and method for improved cache performance is disclosed. In one embodiment, a processor with a cache having a dirty cache line subject to eviction may send the dirty cache line to an available replacement block in another processor's cache. In one embodiment, an available replacement block may contain a cache line in an invalid state. In another embodiment, an available replacement block may contain a cache line in an invalid state or in a shared state. Multiple transfers of the dirty ca...

A system and method of satisfying read and write requests is used in a system having a plurality of cache-equipped processors coupled into a hypercube structure via buses, where each processor is simultaneously coupled to other processors on other buses via gateway means. Read and write requests for a line of data from any of the processors are satisfied by forwarding an update or invalidate request for a given data block containing the line of data requested. This request is forwarded to all ot...

Any number of sorted lists are efficiently partitioned into P lists, where P represents the number of processors available to sort the resulting lists. When given a large list to sort, the list is initially divided into P lists, and each processor sorts one of these lists. The lists are then exactly partitioned so that each of the elements in the new consecutive partitioned lists have values no smaller than any of the elements in the lists before it, nor larger than any of the elements in the li...

The storage of data line in one or more L1 caches and/or a shared L2 cache of a chip multiprocessor is dynamically optimized based on the sharing of the data line. In one embodiment, an enhanced L2 cache directory entry associated with the data line is generated in an L2 cache directory of the shared L2 cache. The enhanced L2 cache directory entry includes a cache mask indicating a storage state of the data line in the one or more L1 caches and the shared L2 cache. In some embodiments, where the...

An array of streaming multiprocessors shares data via a shared memory. A flushing mechanism is used to guarantee that data required for dependent computations is available in the shared memory.

A parallel processing approach for use in multiple hypothesis tracking applications that provides partitioning and load balancing to achieve greater processing efficiency. The present invention comprises a plurality of processors that are each coupled to a shared memory, and which communicate to a central database stored in the shared memory. The central database is organized as a collection of radar tracks. Radar data is supplied to the processors as an input data stream organized in terms of r...

A computer system includes a cache memory which is shared by multiple processors. The cache memory is divided into a plurality of regions. Each of the processor is exclusively associated with one or more of the regions. All the processors have access to all regions on hits. However, on misses, a processor can cause memory allocation only within its associated region or regions. This means that a processor can cause memory allocation only over data it had fetched. By such arrangement, the "cross-...

An arbiter is provided for resolving contention on synchronous packet switched busses, including busses composed of a plurality of pipelined segments, to ensure that all devices serviced by such a bus are given fair, bounded time access to the bus and to permit such devices to fill all available bus cycles with packets. Flow control for shared memory multiprocessors is readily implemented with this arbiter because the arbiter supports different types of arbitration requests and the prioritizatio...

A method of reducing memory latency associated with a read-type operation in a multiprocessor computer system is disclosed. When a requesting processing unit issues a message indicating that it desires to read a value from an address of a memory device of the computer system, each cache snoops an interconnect to detect the message, and transmits a response to the message, wherein a shared intervention response is transmitted to indicate that a cache containing an unmodified value corresponding t...