A shared memory multiprocessor having a packet switched bus for transferring data between a plurality processors, I/O devices, cache memories and main memory employs a bus protocol which permits multiple copies of data to be updated under the control of different processors while still ensuring that all processors and all I/O devices have access to consistent values for all data at all times.

In a distributed-memory multiprocessor system in which a plurality of processors have their respective memories, some of the processors are placed in redundant execution of writing into a virtual storage space. At redundant execution, each processor makes a determination of whether or not it is to perform the writing. As a consequence, only a single processor is allowed to write data into the virtual storage space, which solves the data transfer overhead problem. If a processor that has a memory...

According to a preferred embodiment, a method of sorting a list of elements with duplicate entries using multiple processors is disclosed. Using "P" processors, a list of elements is split into P lists and each processor pre-sorts a list. All pre-sorted lists are lined up to form a partitioning table, with each pre-sorted list making up a column in the table, and the first element from each pre-sorted list making up the first row in the table, and the second element from each pre-sorted list mak...

The present invention discloses an apparatus and method for maintaining the coherence of data within a shared memory network including a plurality of nodes. The system utilizes processors monitoring the occurrence of particular processing events within a local memory storage area. Upon the detection of events indicating the change of status of a particular group of data, a comparison is made between a modified copy of the group of data and a clean copy of the group of data to detect any modifica...

In a memory device shared among processors, a communication buffer having a size requested by the processing program of the origin of sending is dynamically secured. After the communication buffer has been secured, the send program writes a message to be conveyed to the receive program into the above described communication buffer and asks the send OS to perform sending. The send OS sends a communication ID having "1" set in the bit position corresponding to the receive program. On the basis of ...

A high flow-rate synchronizer/scheduler apparatus for a mutiprocessor system during program run-time, comprises a connection matrix for monitoring and detecting computational tasks which are allowed for execution containing a task map and a network of nodes for distributing to the processors information or computational tasks detected to be enabled by the connection matrix. The network of nodes possesses the capability of decomposing information on a pack of allocated computational tasks into me...

A method of verifying a protocol for a shared-memory multiprocessor system for sequential consistency. In the system there are n processors and m memory locations that are shared by the processors. A protocol automaton, such as a cache coherence protocol automaton, is developed. The protocol automaton and a plurality of checker automata are provided to a model checker which exhaustively searches the state space of the protocol automaton. During the search, the plurality of checker automata check...

A method (and apparatus) of determinstically replaying an observable run-time behavior of distributed multi-threaded programs on multiprocessors in a shared-memory multiprocessor environment, wherein a run-time behavior of the programs includes sequences of events, each sequence being associated with one of a plurality of execution threads, includes identifying an execution order of critical events of the program, wherein the program includes critical events and non-critical events, generating g...

A method and apparatus for a large-way, symmetric multiprocessor system using a bus-based cache-coherence protocol is provided. The distributed system structure contains an address switch, multiple memory subsystems, and multiple master devices, either processors, I/O agents, or coherent memory adapters, organized into a set of nodes supported by a node controller. Each of the processors may have multiple caches. The address switch connects to each of the node controllers and to each of the memo...

A method of executing a transaction task within a transaction processing system includes, responsive to an event, the steps of identifying a workflow associated with the event. A transaction task, that at least partially executes the workflow, is distributed to an available thread within a pool threads operating within a multiprocessor system, that may be a Symmetrical Multiprocessor (SMP) system.