A multiprocessor system includes a plurality of central processing units (CPUs), which have a main storage in common, and a key storage for storing therein control information for storage protection of, reference to, and change in the main storage. Each CPU is provided with the key storage, the CPUs are connected by interface lines so as to form a ring-like combination, a CPU in which a key access request is generated, carries out the key processing for its own key storage and supplies the inter...

This disclosure describes a snooping coherency protocol for a multiprocessor network wherein every processor has its own private cache and bus interface means and the network is connected via a common system bus. Each processor has its own cache directory and image directory that duplicate each other non-atomically. The snooping protocol utilizes the duality of directories coupled with the non-atomicity of directory updates to maximize processor-cache availability and minimize processor-cache ac...

A computing apparatus has a mode selector configured to select one of a long-bus mode corresponding to a first memory size and a short-bus mode corresponding to a second memory size which is less than the first memory size. An address bus of the computing apparatus is configured to transmit an address consisting of address bits defining the first memory size and a subset of the address bits defining the second memory size. The address bus has N communication lines each configured to transmit one...

A method of maintaining cache coherency in a shared memory multiprocessor system having a plurality of nodes, where each node itself is a shared memory multiprocessor. With this invention, an additional shared owner state is maintained so that if a cache at the highest level of cache memory in the system issues a read or write request to a cache line that misses the highest cache level of the system, then the owner of the cache line places the cache line on the bus interconnecting the highest le...

A method for operating a shared memory computer system to reduce the latency times associated with lock/unlock code sequences. The computer system includes a shared memory and a plurality of processors. When one of the processors wishes to modify a shared variable stored in the shared memory, the processor must first request and receive a lock from the shared memory. The lock prevents any other processor in the computer system from modifying data in the shared memory during the locked period. In...

An apparatus, method and medium for implementing fault-tolerant three-phase flushing for database transaction commits in a cluster including multiple nodes of shared-memory processors. The apparatus, method and medium include executing the primary of a commit coordinator process pair on a first of the nodes and executing its backup on a second node, executing the primary of a resource manager process pair on a third node and executing its backup on a fourth, and executing the primary of a Log pr...

A cache coherence protocol for a multiprocessor system. Each processor in the system has an associated cache capable of storing multiple word data lines. The system also includes a plurality of main memory modules, each having an associated distributed global directory storing directory information for lines stored in the associated main memory module. Each main memory module is connected to each processor by means of a multi-stage interconnection network. When a processor attempts to over-write...

In multiprocessor machines and chip multiprocessor systems in particular, the object of the present invention is to reduce data communication between the LSI chip and external components and to avoid restrictions in communication volume resulting from the LSI pin count. Sets in tag and data blocks of a shared cache include a shared bit S. When data is replaced for a cache miss, the contents of the shared bit S are checked and the side with the shared bit S set to 0 in the tag and data block is s...

A disk unit control apparatus (DKC) comprises a cache memory provided between a CPU and an external memory (DKU) storing the information exchanged with the CPU, the cache memory holding temporarily copies of the information stored in the DKU. A request from the CPU for access to the information stored in the DKU is met as far as possible by use of the information held in the cache memory. First transfer routes of information between the CPU and the cache memory is greater in number than second t...

The present invention enables efficient matrix multiplication operations on parallel processing devices. One embodiment is a method for mapping CTAs to result matrix tiles for matrix multiplication operations. Another embodiment is a second method for mapping CTAs to result tiles. Yet other embodiments are methods for mapping the individual threads of a CTA to the elements of a tile for result tile computations, source tile copy operations, and source tile copy and transpose operations. The pres...