An output buffer with a controlled high logic state prevents the output voltage from increasing when the supply voltage, Vcc, increases. A fast low-to-high logic transition is achieved by using a pumping circuit to improve the low-to-high transition rate. However, when the Vcc voltage rises past a threshold value, the pumping circuit will only be enabled during a portion of the transition time. This prevents the output level from increasing beyond its nominal value. Because the output voltage is...

An output scanner for recording an image on a radiation sensitive medium comprises an at least part cylindrical support which carries the medium in use, the medium facing radially inwardly. A scanning unit is positioned radially inwardly of the support and has a generator for generating a plurality of modulated radiation beams, the beams being modulated with respective image information, and a reflector for reflecting the two beams onto the medium at respective, different positions. Optics focus...

An output circuit serving as an interface between an LSI and an external LSI, even though the power voltage of the external LSI is not less than the withstand voltage of the gate oxide layer of each of the MOS transistors forming the output circuit, can supply, from the output unit thereof, a signal of which amplitude is equal to the power voltage of the external LSI without a voltage not less than the withstand voltage above-mentioned applied to the gate oxide layer of each of the MOS transisto...

The object of the present invention is, in a power control device including an auxiliary circuit that is connected in parallel to an output circuit and controls an adjusting current smaller by a substantially constant ratio than an output current, to control the ratio of the output current to the adjusting current at a constant level by controlling the output circuit and the auxiliary circuit so that the potentials of the corresponding terminals agree with each other. As a means for attaining th...

An output circuit which can minimize the delay in combining two clocks comprises a multiplexer with a flip flop connected to one input and a clocked latch connected to the other. The clocked latch is transparent during one clocking state so that changes to its input appear directly at its output.

An integrated circuit output driver provides high speed communication, such as between integrated circuits in spite of appreciable interconnection capacitance. The output driver reduces the current sourced or sunk from a circuit node during its switching as its voltage approaches power supply or ground voltages. This reduces the voltage swing and ringing at the circuit node during high speed communication, thus reducing switching time. The output driver provides full voltage swing under quiescen...

An output apparatus which includes a font information memory for outputting a pattern on the basis of information from a host computer, a selector for designating an attribute of fonts, and a dot printer for outputting a table of the fonts having the attribute designated by the selector.

The turn-on time of an output transistor is minimized to suppress the average value of the load current, and the load is electrically charged with an intermediate potential prior to outputting data to suppress the instantaneous value of the load current. The output circuit holds the load in an open state when a predetermined reset signal has a first logic level, and drives the load from a high-potential side power source or a low-potential side power source depending on the logic level of the ou...

There is provided an output apparatus in which an output resolution can be changed and a memory medium including character information of printing dot patterns is detachable. The memory medium has holding means for storing and holding output density information of dot patterns of characters stored in the memory medium. The apparatus comprises in one embodiment: reading means for reading out the output density information from the memory medium; and changing means for changing the output resoluti...

An output buffer generates "1" or "0" data based on control signals VA and VB transferred from memory cells through a DQ gate in a DRAM. The output buffer has first and second discharge circuits, and a first output transistor (PMOS Transistor). The second discharge circuit stops discharging the gate of the first output transistor after the voltage on the gate drops below the threshold voltage of the first output transistor and the first output transistor turns ON. After this time, only the first...