A detection circuit for providing an error signal corresponding to the phase difference between applied input signals is described comprising a balanced multiplier input section for receiving the input signals and having a pair of outputs; a first switching circuit responsive to a switching signal for commutating the outputs of the multiplier section between first and second circuit nodes; a current turnaround circuit coupled between the first and second circuit nodes and third and fourth circui...

This invention relates to a circuit for detecting the phase of an AC signal of frequency f. The signal is applied to two mixers one of which mixes the AC signal with a first signal of frequency f to generate a signal I and the other of which mixes the AC signal with a second signal of frequency f which is 90 degrees out of phase with the first signal to generate a signal Q. The I and Q signals are digitized and the log of the absolute value of each of the digitized signals is generated. The log ...

A phase comparator included in a phase locked loop (PLL) for comparing two input signals with respect to phase to thereby determine their phase difference includes two multipliers and two low-pass filters for producing a sine component signal and a cosine component signal which are associated with the phase difference. A discrimination signal representative of a polarity is generated on the basis of one of those two component signals, and a phase error signal is generated on the basis of the oth...

A phase comparator accepts two streams of digital pulses, one being a reference signal and the other a test signal, and generates an output signal indicative of the phase difference. The phase comparator can be implemented as a four-state device or higher, and thus exhibits a wide phase capture range, i.e. multiples of 360.degree., and can provide a stable, predictable and linear output signal when the two input signals are in lock. It is therefore very suitable for use in a phase locked loop in...

A phase detector for indicating the magnitude of a phase difference between two electrical signals applied to it, is provided with means for introducing a deliberate phase shift into one of the signals so that the measured phase difference never closely approaches 0.degree. or a multiple of 360.degree.. The detector is capable of providing a smooth output signal over a very wide range of phase difference which can exceed many multiples of 360.degree.. Furthermore, the phase comparator is never r...

An output of a flip flop (21) at a first stage is connected to a D-input of a flip flop (22) at a second stage, and an inverted-output of the flip flop (21) is connected to a D-input of a flip flop (23) at a third stage. A reference clock BCK is supplied to the D-input of the flip flop (21), and an oscillation clock OCK is inputted to each T-input of the respective flip flops (21) to (23). An XOR of the reference clock BCK and an output signal Q1 of the flip flop (21), and a logical product of a...

A phase comparator that is configured with a fewer number of gates in an ECL circuit configuration as compared to conventional phase comparator circuits. The phase comparator also operates with lower current consumption, and can achieve a suitable detection of small phase difference by substantially suppressing the influence of spike noises which may arise in the signals input to the phase comparator.

A phase monitor for a short-circuited asynchronous three-phase motor comprises a first and a second sensing unit, both of which are connected to a supply voltage line to the motor in order to sense the voltage conditions on the line, and a control switch which is controlled by the two sensing units and connected in a control circuit for a supply voltage switch for the motor, connected in the supply voltage line. When the supply voltage line is connected to a supply voltage source, the first sens...

A phase shifter with a phase shift primarily independent of frequency includes first and second quadrature hybrids, a delay and a ganged switch. A first path includes an input into the delay, the delay output being connected into the first quadrature hybrid. The corresponding isolated terminal of the first quadrature hybrid forms the output of the first path. A second path includes an input to the second hybrid quadrature with a terminal thereof as an output. Two remaining terminals of the secon...

A phase shifter includes first and second series-connected resistor circuits each including first and second resistors and each interposed between each one of two input terminals and each one of two output terminals, and includes capacitors each interposed between each one of medium points of the series-connected circuits and each one of two output terminals. The phase shifter also establishes a relationship of RgRl=R.sup.2 where the value of the first resistor is Rg/2, the value of the second r...