A phase converter that converts single phase AC electric power to balanced three phase AC power. Two input terminal connected to the output of a single phase AC power source connect directly to two output terminals of the converter. The phase converter has two serially connected storage capacitors with a common connection, a charging circuit for controlled charging the storage capacitors and an output circuit for controlled discharge of the storage capacitors to provide single phase AC power to ...

This invention provides a phase splitter device that generates in-phase and quadrature outputs that have a phase difference of substantially a phase set value (e.g., 90.degree.) and an amplitude difference of substantially an amplitude set value (e.g., zero). A first feedback loop controls the phase difference between the in-phase and the quadrature outputs while a second feedback loop controls the amplitude difference between the in-phase and quadrature outputs. The phase splitter device contro...

A phase splitter is disclosed for preventing a timing loss from a presentation timing mismatch of a clock signal of a phase equal to a reference signal and a clock signal of a phase inverted from the reference signal, including a semiconductor device for providing a signal of the same phase and a signal of an inverted phase with respect to a received reference signal, the semiconductor device including a first and a second transmission gates for receiving the reference signal and an inverted ver...

Apparatus for measuring the phase of a predetermined incoming data sequence comprising, sampling means operable under control of a sampling clock to sample the incoming sequence at a frequency not equal to an integer multiple or divisor of the data rate of the sequence, test means operable to record a plurality of the samples in a time-ordered sequence, reference means operable to store a copy of at least a portion of the predetermined digital data sequence, comparison means operable to compare ...

The present invention provides a phase detector without dead zone, which can reduce clock jitter and provide higher tolerance for data random jitter. It can output a plurality of control signals (up,dn) through the function of a plurality of multi-phase clock signals to detect the transition edge of data signals. Therefore, the relation between the phase error .theta..sub.e and the voltage Vd of a phase-locked loop can be adjusted to be nearly linear dependent. In this way, the phase-locked loop...

A circuit comprising a pump-up circuit and a pump-down circuit. The pump-up circuit may be configured to generate a pump-up signal in response to (i) a data signal and a clock signal. The pump-down circuit may be configured to generate a pump-down signal in response to (i) the data signal, (ii) the clock signal, and (iii) a quadrature of the clock signal.

Apparatus for producing an oscillating signal in a predetermined phase relationship with an input signal which generates its output signal by mixing in variable proportions two or more reference oscillating signals. Preferably the reference signals should be in quadrature relationship and have approximately the same frequency as the desired output, but this is not essential. The output signal may be desired to be in phase with the input signal or to have a predetermined phase offset. In a furthe...

The present invention relates to a reflection diode phase shifter that achieves amplitude equality between phase shifts of incident energy. Amplitude equality is achieved by placing a resistor R to ground in parallel with the transmission lines connecting a four-port coupler to symmetric reflection terminators having an impedance that is varied by a diode. The resistor is placed at a point on the transmission line having the lowest voltage when the greatest power loss is realized by the phase sh...

A phase detector for a phase locked loop frequency synthesizer, in which frequency-divided signals from a variable frequency oscillator and a reference oscillator are used to trigger respective ramp waveform generators, and a sample pulse generator is arranged to be responsive to the reference ramp waveform to provide sample pulses centered at the mid-point of that ramp waveform to respective sample and hold circuits, the relative phases of the ramp waveforms being determined from the sampled an...

A phase comparison circuit for producing a voltage error signal proportional to the difference in phase between a reference signal and an input signal. The reference signal is in the form of a sawtooth wave signal having a fixed frequency and fixed period. The input signal may vary widely in frequency. Sample pulses are derived from the input signal and are used to sample the ramps of the sawtooth signal to produce the error signal. When the frequency of the input signal differs from that of the...