A priority encoder, for determining one of a plurality of channels requesting service simultaneously, includes a selecting circuit provided between a channel determining circuit and a channel memory. The determining circuit selects one of channels to be served in a fixed priority mode or rotating priority mode and generates a next channel signal. The channel memory supplies a stored channel signal, which indicates a previously served channel, to the determining circuit for determining the one of...

A low voltage swing priority encoder comprising pass cells to provide differential voltages indicative of the leading one of a binary tuple. A tree structure with bypass paths allows for the minimization of the number of pass cells in a signal propagation path so as to reduce signal delay. The pass cells are responsive to control voltages indicative of various Boolean functions of the binary tuple, and a pulse voltage signal is applied to the pass cells. In response to the control voltages and t...

A priority selector of a system including a plurality of processors and a shared source commonly used by the processors sets a priority of requests supplied from the processors for using the shared source and supplies a use permission to a single processor. The priority selector has a plurality of lock request priority setting circuits corresponding to the processors and a request selector. When a contention occurs between an own request from a processor and other request from another processor,...

A priority encoder using a MOS array and neural network concepts is composed of an input side neuron group, an output side neuron group, a synapse group, a bias group and inverters. The encoder is simple in its construction and fast in its operating speed compared with the conventional priority encoders utilizing simple Boolean logic.

A priority encoder includes static, tree-like product circuitry that responds to input signals, providing subset signals for subsets of the input signals. The subset signals can be for power-of-two subsets such as 1, 2, 4, 8, etc. input signals. The priority encoder also includes dynamic, tree-like priority circuitry that responds to the subset signals, providing priority signals, each indicating whether a respective input line is asserted and has priority. Each output line of the priority circu...

Apparatus and a method are disclosed for providing a priority queuing arrangement in the transmit direction in Inter-Working Units (IWUs) that permits Frame Relay data packets or ATM cells from channels that have contracted for a particular level of bandwidth service to be provided that service, even during heavy traffic periods when there is contention for resources in the IWU.

A priority encoder for a content addressable memory (CAM) includes a thermometer circuit in which the priority of multiple data inputs is determined at the transistor level. Matching outputs from a CAM are fed to the priority encoder. The priority encoder is divided into a number of segments. A signal indicating a match in a higher priority segment causes lower priority segments to be disabled. Matching inputs are prioritized by way of a parallel arrangement of transistors coupled to NOR gates. ...

Priority binding enables a one-to-many mapping of a target to a source without requiring complex code development by the specification of one or more binding statements. During runtime, these bindings are evaluated. The highest priority binding that evaluates successfully is executed, controlling the two-way transfer of information between source and target. During execution, all possible data binding pathways are monitored. If a binding that has a higher priority than the existing binding evalu...

A priority valve that connects either of two inlet ports, whichever has the highest fluid pressure therein, with an outlet port. The valve includes a flexible diaphragm that carries a valve element alternately engageable with a pair of valve seats for controlling the flow of fluid between the inlet ports and the outlet port.

In a priority circuit, priority processing is rapidly performed without lowering the voltage level of a signal propagated through serially connected transistors. When the priority circuit is placed in a non-operational state by turning off an NMOS transistor in accordance with a precharge enable signal, potentials on propagating signal nodes and a HIT output terminal are precharged to H potential by PMOS transistors used for precharging. Therefore, when the NMOS transistor is turned on and the p...