The carry-line comprises a plurality of MOSFETs connected in series. MOSFETs precharge each node when they receive precharge signals /PR. In the case of high-order priority designated mode, when input signals are given for turning on MOSFETs located between one end of the high-order bit side of the carry-line, the control circuit discharges the intermediate node separately from the carry-line. In the case of low-order bit priority designated mode, when input signals are given for turning on MOSF...

A circular priority encoder includes a linear priority encoder that receives a plurality of requests of ranks 1 to n on corresponding request lines. The encoder acknowledges on an acknowledgement output the request of the lowest rank among the requests it receives; a mask register is connected to transmit to the linear encoder only the requests whose ranks are determined to be active by the ranks of active bits of a mask contained in the mask register. A mask generator provides the mask register...

A priority system is disclosed in which "runt" signals, i.e., signals not conforming to the designed-for waveform, do not generate erroneous priority signals. A tunnel diode detector is coupled intermediate each request receive flip-flop that receives the associated request receive signal and the associated priority select flip-flop that holds the associated request receive signal. The tunnel diode detector switches or not switches with no uncertain ringing or oscillating conditions providing po...

Overfeed prevention method and apparatus operative during the purging of a pneumatic line which, between purges, conveys fiber material from a source to one or more of a plurality of stations. Whenever a station indicates a demand for fibers, control circuitry causes fibers to be supplied to that station and after all the demanding stations have been so supplied, the line is purged of fibers by operating at least one (preferably the last fed one) of only those stations which received fibers duri...

A priority control circuit for establishing connections between a data handling system element and a number of subsystems wherein request signals from subsystems are scanned and granted service in a sequence which is determined by their position in a priority ranking order. The scanner returns to the beginning of the order immediately after a request has been granted, the subsystem just serviced being bypassed in the next scan until all of the remaining request signals have been processed. Each ...

A system for automatically maintaining a record for an order of data priority of data stored in locations of an associative memory which compares the data stored in the locations with newly received data to generate a comparison output and where the order of priority is based on usage of data, comprising a read only memory a bit configuration reflecting an algorithm, connected from the associative memory for generating a first set of signals defining the least recently used location of the assoc...

A data processing system including a dual ported main memory that can be accessed by I/O controllers via a common bus or directly by the central processing unit. The main memory is comprised of a volatile RAM array that requires periodic refreshing to prevent loss of information. Access to the main memory is controlled by a priority resolver that awards access to the main memory on the basis of predetermined priority levels assigned to CPU, I/O and refresh requests. The priority resolver produce...

A processor architecture comprises a priority processing unit (20), a priority memory (30), an instruction set memory (40), and an instruction execution unit (50). The priority processing unit (20) generates priority values and stores them in priority memory (30). Each priority value is associated with an instruction stored in instruction memory (40). Priority processing unit (20) causes the instruction associated with a particular priority value to be outputted to instruction execution unit (50...

A circuit for controlling the provision of electrical energy to an accessory circuit in accordance with an established priority and the energy demands placed upon the remainder of the system by the other accessories powered therefrom is disclosed herein. The circuit includes a control transistor which provides an electrical interconnection between the vehicle bus bar and the accessory and its accessory battery. When the demands placed upon the remainder of the electrical circuit are high the con...

Described is a sequence interlock generator and priority apparatus combination suitable for use in a storage control system for a two-level storage, wherein the storage system includes a high-speed storage against which requests for data are processed and a slower, larger-capacity main storage. Requests can be received and serviced concurrently at a plurality of request ports in the system where they are buffered in request stacks. A tag storage serves as an index to the data currently resident ...