A priority mixer control for a multi-microphone audio system comprises a threshold signal generator that develops a scanning D.C. threshold signal starting at a maximum level for a time T1 and then decreasing in amplitude as a function of time. Each microphone channel is provided with a control channel including a comparator that compares the microphone signal, as an A.C. signal, with the threshold signal, and that switches the microphone channel to "on" condition when the microphone signal exce...

A priority control system for determining a priority order of bus requests in an information processor includes a main group of first bus request sources; an auxiliary group of second bus request sources provided in one of the first bus request sources; and a sampling unit responsive to the bus use conditions to effect sampling to check if there is a bus request for either said main or said auxiliary group.

A flow control valve in a hydraulic system having a single source of pressurized fluid. The flow control valve provides priority of flow for predetermined actuators and pressure control for a plurality of hydraulic actuators.

A circuit for tabling and processing interrupts on a priority basis including a separate table for each level of interrupt priority.

A priority order decomposing apparatus converting binary data of a plurality of bits into data wherein "1"s other than "1" of the bit whose priority order is the highest are removed, a circuit for checking whether or not "1" exists is installed for each group of bits taken as a unit of converting process. When "1" exists, this is transmitted directly to the low-order-bit side to immediately set the lower-order bits to "0". This permits the operating speed to be made faster.

A special purpose circuit unit, responsive to a special BBD instruction, provides for more efficient execution of program branches required in poll and test type routines used by data processors. This unit can easily be added to almost any contemporary processing system to speed up performance of priority branch operations. It includes: a stack of registers loadable with branch addresses designating locations of branch target instructions, an input register for holding bits representing branch c...

The invention describes a system for and a method of creating and using dependencies to determine the order of servicing transaction requests in a multiple queue environment. When more than one outstanding transaction affects the same memory location, dependencies are established to ensure the correct sequencing of the competing transactions. In a preferred embodiment the dependency is configured to ensure that, as each request is inserted, other outstanding requests are checked to determine if ...

The invention relates to a priority valve for a hydraulic installation having a main circuit and an auxiliary circuit. The priority valve has a slide member which primarily has a controlled throttle for dividing the supply fluid between the main and auxiliary circuits in accordance with the priority demands of the main circuit. The priority valve has a flow path leading to the auxiliary circuit which has throttle elements in series which provide pressure drops in steps to minimize cavitation whe...

In a focus detection system for detecting focus condition of an objective lens, there is disposed a pair of photo sensor arrays each having a plurality of photo cells lined up in one diection to receive a first image and second image passed through respectively a lens system and the photo sensor arrays produce first original signal groups and second original signal groups each signal groups corresponding to light intensity of the images projected thereto. A processing device processes the origin...

A dual priority hold register enables the transfer of data to memory ports having serial priority in accordance with two stages of priority. First, all latches of a high priority sector of the register are cleared. Then, the highest priority latch of the low priority sector of the register is cleared, while the latches of the higher priority register are loaded with further data. Following clearance of the low priority latch, all latches of the higher priority register are cleared once again, fo...