
In one aspect of the invention, a semiconductor chip having an array of memory cells and peripheral integrated circuitry comprises: CMOS transistors in the memory array, with the n-channel transistors of the array being formed without LDD regions; and the peripheral integrated circuitry comprising n-channel FET transistors, with such n-channel FET transistors being formed with LDD regions. In another aspect, disclosed is a CMOS process which produces a combination of n-channel MOS transistors ha...











