
Two memory cells each can be entirely fabricated in only two isolation beds. In one embodiment each bed contains one lateral PNP and one vertical NPN transistor in a merged structure. To obtain faster switching speeds, the PNP transistors are cross-coupled as flip-flop transistors while the NPN transistors act as load transistors. A word select signal is applied to forward bias the base-emitter junctions of the NPN load transistors, to thereby generate a potential difference between bit lines co...











