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Two memory cells each can be entirely fabricated in only two isolation beds. In one embodiment each bed contains one lateral PNP and one vertical NPN transistor in a merged structure. To obtain faster switching speeds, the PNP transistors are cross-coupled as flip-flop transistors while the NPN transistors act as load transistors. A word select signal is applied to forward bias the base-emitter junctions of the NPN load transistors, to thereby generate a potential difference between bit lines co...
This invention relates to random elastomeric copolyesters containing units of low molecular weight glycol, poly(alkylene oxide)glycol, dimer acid and 1,2 bis(4-carbomethoxy phenoxy)ethane.
A random time delay fuze includes a fuze base member containing a cylindrl cup guide carrying a slidably mounted cylindrical cup. The cup contains a piston which has a recess slidably mounted on a cylindrical firing pin guide which is also attached to said fuze base and contains a spring biased firing pin. The cup has a ribbon stabilizer, which when exposed to an airstream pulls the cup forward a limited distance, thereby forming a space within the cup between the piston and the cup. The piston ...
The random access memory device of the present invention provides the memory cell array arranged in the form of a matrix. The plurality of memory cells have cross-connected flip-flop circuits. Word driver transistors are provided corresponding to a plurality of word lines, wherein the collector is connected to a high power supply voltage while the emitter is connected to the word line. Moreover, the base of the word driver transistor is connected respectively in common to a selected word line le...
A random vibrations testing device comprising a noise generator the output whereof is connected to an input of a wide-band filter. An output of the wide-band filter is connected directly and through paralleled narrow-band in-phase signal shaping channels to a means for shaping dips and spikes in the spectrum of a signal being shaped, which is electrically coupled with narrow-band opposite-phase signal shaping channels. The means for shaping the spikes and dips in the shaped signal spectrum is de...
The seal consists of a hollow stud member which is welded to the enclosure to be secured and a cap member which holds the enclosure cover in place when secured to the stud. The cap member has a body section and a pin element extending from it. The pin element has an end portion that is shaped so as to be permanently secured once it enters a receiving element in the stud member. The cap member further has a random identity element, such as a randomly wound coil mounted in a cavity within the cap ...
Pseudo-random numbers (PRNs) have great importance in data processing and encryption. The standard technique for generating PRNs on computers at the present time involves software implementation of recursively computing PRN.sub.n+1 =(PRN.sub.n)(b) mod M, in real number field which means that a relatively slow and involved multiplication must occur for each PRN, and each PRN calculation is strictly subsequent to previous PRM calculations. This disclosure shows a systolic multiplier implemented by...
The static random access memory reduces the access time thereof and reduces the power consumption thereof during its time of operation, and employs a circuit arrangement such that not only is the logical amplitude of each bit line diminished during a read-out operation, but the bit line is precharged after a write operation is accomplished during a write operation.
A random number generator (RNG) uses an edge-triggered D-type flip-flop with a high frequency square wave having an approximately 50 percent duty cycle connected to a data input terminal and a low frequency square wave connected to a clock input terminal, a five-state counter, five two-input AND gates, five exclusive-OR gates, and five shift registers. An essentially truly random number is generated at the RNG output terminals. Probability biases due to both variations in the 50 percent duty cyc...
A bipolar random access memory array including "end of write shut down circuit means" coupled to the write circuit means is disclosed. The "end of write shut down circuit means" is activated by and only functions as the written cell switches state. The "end of write circuit means" is coupled between the opposite bit line and preferably the write transistor of a write circuit of the write circuit means. The use of "the end of write circuit means" improves the overall operation of the memory and i...
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