
This disclosure relates to an MOS random access memory array which utilizes a very small memory cell having a single MOS device and a small size, high capacitance, semiconductor capacitor device connected together to form one bit or memory cell of an MOS dynamic, random access memory array. Preferably, either the source or drain region of the MOS device is connected to the semiconductor portion of the semiconductor capacitor device which is of the electrode-insulator-semiconductor type. The semi...











