A versatile binary register which has control means for selectively setting the register to the one's and two's complements in response to first and second control signals, respectively. In addition, alternate application of the first and second control signals causes the register to function as a counter which operates in the forward mode if the first and second control signals are applied in a given sequence and/or operates in the reverse mode if the signals are applied in an opposite sequence...

A pocket register for containing a supply of manifolding material comprising a container for said material, a writing surface mounted within the container over which a strip of the material may be extended after being withdrawn from the interior of the container, means on the writing surface for engaging sheets of transfer material to be interposed between superposed portions of several sheets of manifolding material and adapted to limit extension of the withdrawn sheets, and a substantially ope...

An electronic shift register used with a source of rectified alternating current, having a positive bus and a ground. A series of shift register stages are serially arranged between a first stage and a last stage, each stage having a silicon controlled rectifier and a transfluxor core associated together. Each silicon controlled rectifier has its cathode connected to ground, and a load is connected between its anode and the positive bus. Each transfluxor has a core and a primary connected to an ...

A doctors register system for hospitals or the like adapted to simultaneously indicate by a signal at a plurality of stations located in different parts of the hospital whether the doctor has checked in or out of the hospital, said system being capable of being actuated from any of the stations each of which has a plurality of units, one for each doctor, with the corresponding units in the stations connected together. Also, means can be provided for altering the character of the signal to provid...

A register device includes a register set group, a switching control unit, a write control unit, a write flag memory unit, and a read control unit. The register set group consists of a plurality of register sets each constituted by a plurality of registers. The switching control unit selects a register set to be used in processing from the register set group in response to a saving/recovery instruction. The write control unit writes data in registers of the register set selected by the switching...

There is disclosed a technique for accessing a register file which comprises defining a first register address as a plurality of bits and using said first register address to access said register file generating a second register address by using a sequence of said plurality of bits with at least one of said plurality of bits supplied via a unitary operator, the unitary operator being effective to selectively alter the logical value of said bit depending on its logical value in the first registe...

A shift register includes bidirectional register units, a direction switching section, a register unit selecting section, and a shift clock supply section. The bidirectional register units are cascaded through first input/output terminals for data shifting and perform data shifting operation. The bidirectional register units have second input/output terminals which separately and directly input/output data. The direction switching section switches the shifting directions of the bidirectional reg...

A shift register for use with a liquid crystal display device includes a plurality of stages. A stage of the shift register includes a first controller, a second controller and an output buffer. The first controller charges and discharges a first node. The second controller charges and discharges a second node and a third node. The output buffer outputs a first output signal in response to the state of the first node and a second output signal in response to the state of the second and third nod...

A multi-phase shift register having a plurality of parallel columns each comprising n stages, where n is preferably greater than 3, and where the data is advanced along each such column by first shifting the data from its n.sup.th stage to the column output terminal, then from the preceding stage to the n.sup.th stage, and then from each of the next preceding stages sequentially to their succeeding stages, until the first stage of the column is reached, whereupon the first stage is emptied of da...

A shift register comprises a series of half-cells with means to transfer the information stored in each half-cell to the next half-cell in the series upon the application of a clock-pulse signal. The circuit is made with just two diffusion steps, obviating the need for an isolation diffusion or a subcollector diffusion.