A shift register is comprised of a plurality of bistable devices with the output of a given bistable device being coupled to the input of the following bistable device by way of a memory circuit which stores a signal indicative of the binary state of the given bistable device in response to the concurrent provision of a shift signal. A reset pulse for each stage of the shift register is also provided in response to the provision of the shift signal. The memory device stores the binary signal for...

A shift register comprising a sequence of shift register elements which each include a first and a second transistor the emitters of which are interconnected and have clock pulse signals applied to them. The base of the second transistor and the collector of the first transistor of each of the shift register elements are interconnected. The base of the first transistors of all the shift register elements are connected to a point of reference potential, whilst the collector of second transistor o...

A speed register intended for thoroughbred racing (flat) is disclosed in a circular slide embodiment and in a straight slide embodiment. The circular slide has a base provided with an annular elapsed time scale and a set of corresponding speed readout scales spaced therealong according to individual race distances. The circular slide embodiment includes a set of rotary discs and cursors secured by a pair of eyelets to accommodate relative shifting movement. The straight slide embodiment includes...

A register board provided with a cabinet having at least one swingable front panel mounted thereon for movement between open and closed position, the panel supporting a series of switches. Each switch has a switch unit carrying an electrical bulb and a translucent lens disposed over the bulb, each lens being selectively depressible to light the bulb therebeneath and each lens being provided with a distinctive indicia. The panel, when swung open, carries all of the switches thereon into exposed p...

Shift registers using the charge-storage effect in individual semiconductors as data stores, including means for applying alternating signals to step the data forward.

A multifunction data storage register is provided having at least one first register cell having a first input multiplexer for selecting between two input signals responsive to one or more control signals and having a first output signal, a first input exclusive not OR circuit having a first input connected to said first output signal of said first input multiplexer and a second input connected to a cell output signal and having a third output signal, a first shift register latch having an input...

A shift register having a simple configuration and improved response and power consumption is disclosed. In the shift register, a plurality of stages are connected to each other in cascade and scanned in a bilateral direction. In the stages, a charger charges a first supply voltage into a first node in response to a clock signal. A discharger discharges the first node in response to a first start pulse or a second start pulse. A scan direction controller is connected between the charger and the ...

A shift register includes a control unit, a signal switching unit and a buffer unit. The control unit determines whether to transfer an input signal from a first input terminal to a first output terminal according to a first control signal, and determines whether to conduct a first pre-defined voltage to a second output terminal according to a second control signal. The signal switching unit uses the signal output from the first output terminal as one of the considerations for determining whethe...

Disclosed is a shift register capable of mitigating gate bias stress. The shift register, including a plurality of stages, includes an output buffer having a pull-up transistor and two pull-down transistors, each with gates connected to different nodes. One of the two pull-down transistors operates during an even frame portion of an LCD operation; and the other of the two pull-down transistors operates during an odd frame portion of the LCD display operation. Alternating operation of the pull-do...

A shift register includes a first node controller disposed at one side of the non-display region, the first node controller controlling a signal state of a first node, at least one pull-up switching device disposed at the one side of the display region, the pull-up switching device outputting an output pulse according to the signal state of the corresponding first node and supplying it to a corresponding gate line, a second node controller disposed at the other side of the display region, the se...