A shift register includes stages shifting an input signal with phase-delayed control signals and first and second supply voltages, and for applying shifted input signals as output signals and as input signals of succeeding stages. Each of the stages includes a first controller selectively applying an input signal and a first supply voltage to a first node between first to third transistors; a second controller selectively applying the first and second supply voltages to a second node between fou...

A quantized voltage is held by a holding circuit or a feedback circuit connected to a quantizing circuit so that a multi-valued voltage is registered. In another embodiment, outputs of bi-stable circuits with stopwise thresholds are added with weights introduced by a capacitive coupling.

A J-K flip/flop type storage register includes an input register and an output register. The input register is active when a clock pulse applied thereto is below a predetermined level defining a logic 0 state and inactive when the clock pulse signal is above the first predetermined level. The output register is active when the level of the clock pulse signal is above a second predetermined level and inactive when the clock pulse signal is below the second predetermined level. There exists a well...

A filter assembly (10) adapted to be secured to a register (18) of the type used for covering a forced air duct outlet (12) in heating/cooling systems is disclosed. The filter assembly (10) removes contaminant particles from air flowing through the forced air duct outlet (12). The filter assembly (10) includes a filter material (33) of permeable and pliable material and an elastic band (34) secured to the filter material (33) for clamping the filter material (33) to the exterior surface (27) of ...

A meter register includes a register body having a rotatable drive shaft coupled thereto. A drive gear is attached to the drive shaft and at least one follower gear is rotatably attached to the register body and coupled with the drive gear. An antenna is provided that includes a first electrically conductive sheet, a second electrically conductive sheet, and an axially extending leg electrically connected to the first electrically conductive sheet and the second electrically conductive sheet. A ...

A shift register is provided, for example, for use in scan and data line drivers for an active matrix liquid crystal display. The shift register comprises X stages, where X is an integer greater than 3. A clock signal generator supplies Y-phase clock signals, where Y is greater than 2. Each of the stages comprises a flip-flop and logic circuit and receives a set enable signal from the immediately preceding stage output. Each stage is set by the leading edge of one of the clock phases in the pres...

An output buffer in each stage of a shift register applies a first clock signal to an output line under control of a first node and a second driving voltage to the output line under control of second and third nodes. A first node controller controls the first node using a start pulse and an output signal of the next stage. A second node controller selectively applies a voltage at a fourth node and the second driving voltage to the second node under control of the first and second clock signals. ...

A shift register minimizing bias stress applied to transistors is disclosed. A shift register including n stages outputting scan pluses that are sequentially delayed in a forward or reverse direction thereof, where n is positive integer and wherein each stage includes: a scan direction controller that provides a first or second voltage to a scan direction control node according to a first or second enable signal and controlling the forward or reverse direction output; a first node controller tha...

A shift register has a plurality of stages which output driving signals, each stage including a pull-up transistor to output a first clock signal in response to a logic value of a Q node; a pull-down transistor to supply a voltage from a first voltage supply source to the output in response to a logic value of a Qb node; a Q node controller to control the logic value of the Q node in response to any one of the previous stage's output signal and the next stage's output signal; and a Qb node contr...

A shift register having an amorphous silicon thin film transistor for decreasing a distortion of the output signal is disclosed. In the shift register having a plurality of stages for shifting an input signal using first and second driving voltages, first and second clock signals and a start pulse, each of said plurality of stages includes an output buffer for selectively applying any one of the first and second clock signals and the second driving voltage to an output line under control of firs...