A shift register which is capable of performing bi-directional scanning is disclosed. The shift register includes first and second voltage input lines to which first and second voltages are input, respectively with the phases of the first and second voltages being opposite to each other; a plurality of stages dependently connected to a plurality of clock signal input lines which input a plurality of clock signals whose phases are sequentially delayed, wherein each stage includes: a scan directio...

Disclosed is an integrated check register and budget register for, among other purposes, the tracking of checks and the tracking of a budget or categorization of expenditures. The integrated register includes a plurality of data sheets longitudinally folded, with the fold forming two quadrants on each side or surface of the paper or data sheet. When adjacent data sheets are unfolded there are four quadrants, which when imprinted with check and budget register indicators, form an integrated check...

The data processing system has a data processing function to perform a data processing by specifying one of a plurality of register groups according to an instruction. The instruction contains information for indicating a change from one register group to another register group and information for specifying a desired one or two or more registers in said register group. This makes it possible to transfer the contents of the desired one or two or more registers to other registers at the time of a...

A multi-port RAM register file adapted for flowing data directly from an input port of the register file to an output port of the register file and for simultaneously writing to a memory location in the register file. In addition to the RAM register, the apparatus includes, in a first embodiment, (1) first and second sets of multiplexers, the first set of multiplexers connected between the register file output ports on the one hand, and, on the other hand, the outputs of the second set of multip...

An apparatus and method are provided for performing a floating point exchange operation in a pipeline microprocessor in zero effective clock cycles. The present invention exploits the pattern of floating point operations common to most floating point software algorithms where floating point exchange operations appear as every other instruction between floating point computational instructions. The apparatus includes translation logic, that pairs the operations directed by a floating point macro ...

A register circuit is disclosed which has input/output data lines, a first register having a first flip-flop and a first transfer gate provided between the input/output terminals of the flip-flop and the input/output data lines and connect them in response to a first selection signal, a second register having a second flip-flop and a second transfer gate provided between the input/output terminals of the flip-flop and the input/output data lines and connect them in response to a second selection...

Vector processing in a computer is achieved by means of a plurality of vector registers, a plurality of independent fully segmented functional units, and means for controlling the operation of the vector registers. Operations are performed on data from vector register to functional unit and back to vector register with minimal delay, rather than memory to functional unit and return to memory with its attendant much greater start-up delays. Data may be bulk transferred between memory and some vec...

A shift register type memory having major and minor loops, wherein the number of bits of the major loop is large enough to permit data of at least two blocks to simultaneously exist in the major loop when one block is constituted of data of bits the number of which is equal to the number of the minor loops, and wherein before a particular block having been transferred out from the minor loops to the major loop is again transferred in to the minor loops after travelling round the major loop, the ...

A transfer sheet of a transfer sheet assembly for use in an Autographic Register System has a coating which embodies a colorless color former. The coating is porous and the colorless color former is retained in the pores of the coating until autographic writing is applied to the uppermost record web of the assembly whereby the colorless color former is squeezed out of the coating onto the upper face of the next record web of the assembly. The record webs of the assembly have a developing recepti...

An interface for transmitting data in either a clock edge triggered synchous transmission mode or an asynchronous transmission mode. An edge triggered register has its input connected to a source of digital data and its output connected to a two-to-one multiplexer. A bypass path connected between the digital data source and the multiplexer is provided around the edge triggered register. The two-to-one multiplexer is selectively actuable to provide either asynchronous transmission by connecting t...